Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, and a memory string extending vertically through the memory stack. The memory string includes a single crystalline silicon plug in a lower portion of the memory string, a memory film above the single crystalline silicon plug and along a sidewall of the memory string, and a single crystalline silicon channel over the memory film and along the sidewall of the memory string.

Abstract: A three-dimensional flash memory is provided, and technique to suppress interference caused by an inter-cell insulation layer in a vertical cell and to form a stable vertical channel layer, a technique to reduce a length of wire than a conventional three-dimensional flash memory for overcoming problems of deterioration of chip characteristics such as operation speed and power consumption and difficulty of wiring technique in the manufacturing process, and a technique to improve horizontal density of channel layers and ONO layers are proposed.

Abstract: A memory die can include an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures vertically extending through the alternating stack. A first layer stack within the alternating stack includes a first staircase region in which the first electrically conductive layers have respective lateral extents that increase with a vertical distance from the substrate to provide first stepped surfaces. A second layer stack within the alternating stack includes a second staircase region in which the second electrically conductive layers have respective lateral extents that decrease with the vertical distance from the substrate to provide second stepped surfaces. The second layer stack can be more distal from the substrate than the first layer stack. Contact via structures can be formed from the top side and the bottom side of the alternating stack.

Abstract: A semiconductor device includes a channel structure arranged on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers arranged on the substrate and surrounding the channel structure, the plurality of insulating layers spaced apart from each other in the first direction; a plurality of first gate electrodes surrounding the channel structure; and a plurality of second gate electrodes surrounding the channel structure. Between adjacent insulating layers from among the plurality of insulating layers are arranged a first gate electrode from among the plurality of first gate electrodes spaced apart along the first direction from a second gate electrode from among the plurality of second gate electrodes.

Abstract: A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel.

Abstract: A semiconductor device includes a lower structure; a stack structure including gate layers and interlayer insulating layers and having an opening; a vertical structure in the opening; a contact structure on the vertical structure; and a conductive line on the contact structure. The vertical structure includes an insulating core region, a channel semiconductor layer covering side and lower surfaces of the insulating core region, data storage patterns between the channel semiconductor layer and the gate layers and spaced apart from each other, a first dielectric layer, and a second dielectric layer. At least a portion of the first dielectric layer is between the data storage patterns and the gate layers, at least a portion of the second dielectric layer is between the data storage patterns and the channel semiconductor layer, and the insulating core region includes first convex portions having increased widths in regions facing the gate layers.

Abstract: Embodiments of a three-dimensional (3D) memory device and method for forming the 3D memory device are provided. In an example, the 3D memory device includes a plurality of conductor layers extending over a substrate, a channel structure vertically extending through the conductor layers to the substrate, and a source structure extending through the conductor layers to the substrate. The channel structure may include a blocking layer having a plurality of blocking portions disconnected from one another. Each of the blocking portions may include (i) a vertical blocking portion under a respective conductor layer, and (ii) at least one lateral blocking portion covering a respective lateral surface of the respective conductor layer. The channel structure may also include a memory layer having a plurality of memory portions disconnected from one another, each of the memory portions under and in contact with the respective vertical blocking portion.

Abstract: A multi-LED structure comprises a first LED and a separate second LED disposed on a common multi-LED native substrate. The LEDs each comprise a common first layer having a cantilever portion and a base portion and a common second layer having a light-emitting emission portion disposed only over the base portion. An LED electrode electrically connects the first LED to the second LED. The cantilever portion extends in a direction different from the base portion or a length of the cantilever portion is less than a distance between the emission portions of the first and second LEDs.

Abstract: Methods for forming channel structures in 3D memory devices are disclosed. In one example, a memory film and a sacrificial layer are subsequently formed along a sidewall and a bottom of a channel hole. A protective structure covering a portion of the sacrificial layer along the sidewall of the channel hole is formed. A portion of the sacrificial layer at the bottom of the channel hole that is not covered by the protective structure is selectively removed. A portion of the memory film at the bottom of the channel hole that is not covered by a remainder of the sacrificial layer is selectively removed.

Abstract: A memory device and method of forming the same are provided. The memory device includes a word line, a bit line, a source line, a channel pillar, and a charge storage structure. The bit line and the source line are disposed on opposite sides of the word line in a vertical direction. The channel pillar penetrates through and is connected to the word line, the bit line and the source line. The charge storage structure surrounds a top surface and a bottom surface of the word line and is laterally sandwiched between the channel pillar and the word line. The channel pillar completely penetrates through and is laterally surrounded by the bit line.

Abstract: A semiconductor device includes: an alternating stack of conductive layers and dielectric layers disposed over a substrate; a channel layer disposed in a through portion, penetrating through the alternating stack; a blocking layer disposed in the through portion, surrounding an outer wall of the channel layer; and a continuous etch stop layer disposed in the through portion, surrounding an outer wall of the blocking layer.

Abstract: The present disclosure provides a method of measuring a plurality of voids in an underfill material of an underfill package. The method includes operations of obtaining a welding angle profile of the underfill package; obtaining a simulated void profile of the underfill package according to the welding angle profile; determining a plurality of high-risk void regions according to the simulated void profile; simulating, according to a selected pressure and a selected temperature of the underfill material, a first high-risk void region of the plurality of high-risk void regions to generate an updated void profile; and determining whether the updated void profile meets a void requirement of the underfill package.

Abstract: Electromagnetic shields for electronic devices, and particularly electromagnetic shields with bonding wires for sub-modules of electronic devices are disclosed. Electronic modules are disclosed that include multiple sub-modules arranged on a substrate with an electromagnetic shield arranged on or over the sub-modules. Bonding wires are disclosed that form one or more bonding wire walls along the substrate. The one or more bonding wire walls may be located between sub-modules of a module and about peripheral boundaries of the module. The electromagnetic shield may be electrically coupled to ground by way of the one or more bonding wire walls. Portions of the electromagnetic shield and the one or more bonding wire walls may form divider walls that are configured to reduce electromagnetic interference between the sub-modules or from external sources.

Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with increased cell density. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. Some embodiments form 3D NAND devices with smaller CD memory holes. Some embodiments form 3D NAND devices with silicon layer between alternating oxide and nitride materials.

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a memory material layer. A vertical stack of insulating material portions can be provided at levels of the insulating layers to provide a laterally-undulating profile to the memory material layer. Alternatively, a combination of inner insulating spacers and outer insulating spacers can be employed to provide a laterally-undulating profile to the memory material layer.

Abstract: A semiconductor device is disclosed including a semiconductor die mounted on a substrate. The substrate includes a pattern of solder balls which is complementary and aligned to a pattern of solder bumps on the semiconductor die. These complementary and aligned patterns of solder balls and solder bumps minimize the lengths of current paths between the solder balls and solder bumps, and provide current paths between the solder balls and solder bumps of relatively uniform lengths.

Abstract: A semiconductor structure includes a first-conductivity-type well located in a semiconductor substrate, a semiconductor active area region located adjacent to the a first-conductivity-type well, a first transistor including a source region, a drain region, a channel region located between the source region and the drain region, a gate dielectric layer located over the channel region and a gate electrode located over the gate dielectric layer, such that the transistor is located on the semiconductor active area region, and a cutoff gate electrode located over the semiconductor active area region, and between the first transistor and the first-conductivity-type well.

Abstract: Embodiments of structures and methods for forming three-dimensional (3D) memory devices are provided. In an example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of stairs each has at least a conductor/dielectric pair extending in a lateral direction. The staircase region includes a drain-select-gate (DSG) cut structure extending along the lateral direction and a vertical direction, and a plurality of support structures extending in the DSG structure along the vertical direction. Of at least one of the support structures, a dimension along the lateral direction is greater than a dimension along a second lateral direction perpendicular to the lateral direction.

Abstract: A memory device can include a strained single-crystalline silicon layer and an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer. A memory opening fill structure extending through the alternating stack may include an epitaxial silicon-containing pedestal channel portion, and a vertical semiconductor channel, and a vertical stack of memory elements located adjacent to the vertical semiconductor channel Additionally or alternatively, a drain region can include a semiconductor drain portion and a nickel-aluminum-semiconductor alloy drain portion.

Abstract: Embodiments described herein relate to a method for manufacturing a 1.5T SONOS flash memory. First, a first polysilicon gate layer is deposited and formed on a semiconductor substrate, then a formation area of a memory gate is defined on the first polysilicon gate layer, polysilicon in the formation area of the memory gate is etched away, and etching is stopped on a gate oxide layer. Next, an ONO layer and a second polysilicon gate layer are sequentially deposited, chemical mechanical polishing is performed on the second polysilicon gate layer, the ONO layer remaining on the top of the first polysilicon gate layer is cleaned away, and then gate structures of a logic device and a 1.5T SONOS device are formed at the same time.