Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, the 3D memory device includes a film stack having a plurality of conductive and dielectric layer pairs vertically stacked on a substrate. Each conductive and dielectric layer pair includes a dielectric layer and a conductive layer. The 3D memory device also includes a staircase region having a first and a second staircase structure formed in the film stack, where the first and second staircase structures each extends laterally in a first direction and includes the plurality of conductive and dielectric layer pairs. The staircase region further includes a staircase bridge connecting the first and second staircase structures.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a 3D NAND memory device includes a substrate, a layer stack over the substrate, a first epitaxial layer, a second epitaxial layer, first array common sources (ACS's), and second ACS's. The layer stack includes first stack layers and second stack layers that are alternately stacked. The first epitaxial layer is deposited on a side portion of a channel layer that extends through the layer stack. The second epitaxial layer is deposited on the substrate. The first ACS's and a portion of the layer stack are between the second ACS's.

Abstract: The current disclosure describes semiconductor devices, e.g., transistors including a thin semimetal layer as a channel region over a substrate, which includes bandgap opening and exhibits semiconductor properties. Described semiconductor devices include source/drain regions that include a thicker semimetal layer over the thin semimetal layer serving as the channel region, this thicker semimetal layer exhibiting metal properties. The semimetal used for the source/drain regions include a same or similar semimetal material as the semimetal of the channel region.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes depositing a cover layer over a substrate, depositing a sacrificial layer over the cover layer, depositing a layer stack over the sacrificial layer, forming a channel layer extending through the layer stack and the sacrificial layer, performing a first epitaxial growth to deposit a first epitaxial layer on a side portion of the channel layer that is close to the substrate, removing the cover layer, and performing a second epitaxial growth to simultaneously thicken the first epitaxial layer and deposit a second epitaxial layer on the substrate. The layer stack includes first stack layers and second stack layers that are alternately stacked.

Abstract: A semiconductor device includes an upper stack structure extending on a lower stack structure, which extends on an underlying substrate. A channel structure extends through the upper stack structure and the lower stack structure. The lower stack structure includes a first lower electrode layer disposed adjacent to an interface between the lower stack structure and the upper stack structure, and a second lower electrode layer disposed adjacent a center of the lower stack structure. The upper stack structure includes a first upper electrode layer disposed adjacent to the interface, and a second upper electrode layer disposed adjacent a center of the upper stack structure. At least one of the first lower electrode layer and the first upper electrode layer is thicker than the second lower electrode layer. At least one insulating layer is disposed between the first lower electrode layer and the first upper electrode layer.

Abstract: A display device is provided. The display device includes: a substrate including a display area including pixels at which an image is displayed and a peripheral area at which the image is not displayed, the peripheral area disposed outside the display area. In the peripheral area, the display device further includes: a plurality of thin film transistors connected to the pixels and with which operation of the pixels is tested, the thin film transistors including gate electrodes arranged separated from each other on the substrate; and a bridge wiring electrically connecting adjacent gate electrodes of the plurality of thin film transistors to each other.

Abstract: A semiconductor storage device includes a memory cell array including a stacked body having insulating layers and conductive layers that are alternately stacked. The memory cell array includes a cell area and a contact area provided adjacent the cell area. The semiconductor storage device includes: a circuit below the memory cell array; a source layer between the memory cell array and the circuit; a first contact in the contact area, and coupled to the circuit; a second contact over the cell area and the contact area; a first wiring extending in a direction intersecting an extending direction of the second contact in the contact area; a second wiring above the second contact, extending along the second contact in the contact area, and connected to the first wiring; and third contacts between the second wiring and the second contact.

Abstract: The present disclosure provides a display substrate which includes: a plurality of pixel units, at least one of which includes a light emitting diode and a drive circuit. The light emitting diode includes a cathode; the display substrate further includes an auxiliary electrode layer including at least one auxiliary electrode. The auxiliary electrode is disposed in at least one of the pixel units. The auxiliary electrode is electrically connected with the cathode of the light emitting diode which is located in the same pixel unit as the pixel unit that the auxiliary electrode is located in, and the auxiliary electrode covers at least a portion of the drive circuit in the pixel unit that the auxiliary electrode is located in. The auxiliary electrode is made of an opaque conductive material, so as to block light irradiated at the portion of the drive circuit that is covered by the auxiliary electrode.

Abstract: Provided are a 3D flash memory and an array layout thereof. The 3D flash memory includes a gate stack structure, a annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base and includes a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrates through the gate stack structure. The first source/drain pillar and the second source/drain pillar are disposed on the dielectric base, are located within the channel pillar and penetrate through the gate stack structure. The first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the channel pillar.

Abstract: A semiconductor memory device includes an electrode structure, a plurality of channel posts, and at least one gate separation layer. The electrode structure includes insulating interlayers and gate conductive layers which are alternately stacked. The channel posts are formed through the electrode structure. The gate separation layer is formed between the channel posts. The gate separation layer separates an uppermost gate conductive layer among the gate conductive layers. Each channel post among the channel posts adjacent to the gate separation layer has a gibbous moon shape in a planar view. The semiconductor memory device further includes a slit structure arranged at both sides of the gate separation layer. The slit structure is formed through the electrode structure. Each channel post among the channel posts adjacent to the slit structure has a gibbous moon shape in the planar view.

Abstract: A semiconductor memory device includes a substrate, a first conductor layer, and a first insulator layer. The substrate includes a first region on which memory cells are provided, a second region on which a control circuit of the memory cells is provided, and a third region separating the first region and the second region. The first conductor layer is above the second region of the substrate. The first insulator layer is above the second and third regions of the substrate. The first insulator layer includes a first portion that is above the first conductor layer and extends along a surface direction of the substrate, and a second portion that is continuous with the first portion and extends along a thickness direction of the substrate from the first portion toward a surface of the substrate in the third region.

Abstract: Embodiments of structure and methods for forming a memory device are provided. In an example, a memory device includes a substrate, a stack above the substrate, a channel structure, and a source contact structure each extending vertically through the memory stack. The source contact structure includes (i) a plurality of first source contact portions each extending vertically and laterally separated from one another and (ii) a second source contact portion extending vertically over and in contact with the plurality of first source contact portions, the second source contact portion being laterally continuous.

Abstract: A vertical memory device includes a channel extending vertically on a substrate. A charge storage structure is disposed on a sidewall of the channel. Gate electrodes are spaced apart from each other vertically and surround the charge storage structure. A first insulation pattern includes an air gap between the gate electrodes. The charge storage structure includes a tunnel insulation layer, a charge trapping pattern, and a first blocking pattern sequentially stacked horizontally. The charge storage structure includes charge trapping patterns spaced apart from each other vertically. Each of the charge trapping patterns faces one of the gate electrodes horizontally. A length in the first direction of an outer sidewall of each of the charge trapping patterns facing the first blocking pattern is less than that of an inner sidewall thereof facing the tunnel insulation layer.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a substrate, a plurality of gate layers, and a plurality of insulating layers. The plurality of gate layers and the plurality of insulating layers are stacked alternately over a first region of the substrate and are stacked of a stair-step form over a second region of the substrate. The semiconductor device also includes a channel structure that is disposed over the first region and through the plurality of gate layers and the plurality of insulating layers. The channel structure and the plurality of gate layers form a stack of transistors in a series configuration with the plurality of gate layers being a plurality of gates for the stack of transistors.

Abstract: Some embodiments include an integrated assembly having a first semiconductor structure containing heavily-doped silicon, a germanium-containing interface material over the first semiconductor structure, and a second semiconductor structure over the germanium-containing interface material. The second semiconductor structure has a heavily-doped lower region adjacent the germanium-containing interface material and has a lightly-doped upper region above the heavily-doped lower region. The lightly-doped upper region and heavily-doped lower region are majority doped to a same dopant type, and join to one another along a boundary region. Some embodiments include an integrated assembly having germanium oxide between a first silicon-containing structure and a second silicon-containing structure. Some embodiments include methods of forming assemblies.

Abstract: A vertical memory device including: a circuit pattern on a first substrate; an insulating interlayer on the first substrate, the insulating interlayer covering the circuit pattern; a bending prevention layer on the insulating interlayer, the bending prevention layer extending in a first direction substantially parallel to an upper surface of the first substrate; a second substrate on the bending prevention layer; gate electrodes spaced apart from each other in a second direction on the second substrate, the second direction being substantially perpendicular to the upper surface of the first substrate; and a channel extending through the gate electrodes in the second direction.

Abstract: According to principals as disclosed herein an organic, light emitting diode assembly is provided having a first electrode. An electron injection layer is adjacent to the first electrode. A first electron transport layer composed of inorganic material is adjacent to the electron injection layer. A second electron transport layer composed of organic material is adjacent to the first electron transport layer and in contact with an organic light emitting material layer. The organic light emitting material layer is in direct, abutting contact with the second electron transport layer. A hole transport layer is adjacent to the organic light emitting material layer and a second electrode is adjacent to the hole transport layer.

Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises a cavity therein that comprises a stair-step structure. Sidewalls of the cavity and steps of the stair-step structure are lined with an insulator material. Insulative material is formed in the cavity radially inward of the insulator material. An upper portion of the insulative material is removed from the cavity to leave the insulative material in a bottom of the cavity over the stair-step structure. After the removing, insulating material is formed in the cavity above the insulative material. Other embodiments, including structure independent of method, are disclosed.

Abstract: A semiconductor device includes; a memory stack disposed on a substrate and including a lower gate electrode, an upper gate stack including a string selection line, a vertically extending memory gate contact disposed on the lower gate electrode, and a vertically extending selection line stud disposed on the string selection line. The string selection line includes a material different from that of the lower gate electrode, and the selection line stud includes a material different from that of the memory gate contact.

Abstract: An illumination apparatus including a transparent substrate, an opposite substrate and an electroluminescence structure disposed between the transparent substrate and the opposite substrate is provided. The transparent substrate has a first region and a second region adjacent to the first region. The electroluminescence structure is disposed on the transparent substrate. The electroluminescence structure includes a first electrode disposed in the first region, an optical adjusting layer disposed in the second region, an organic electroluminescence layer disposed above the first electrode and the optical adjusting layer and a common electrode disposed above the organic electroluminescence layer. The optical adjusting layer is disposed between the organic electroluminescence layer and the transparent substrate.