Abstract: A chip structure includes a substrate and a stress buffer layer. The substrate has a first surface and a second surface opposite to the first surface. The stress buffer layer is disposed on the periphery of the substrate and located in at least one of the first surface and the second surface of the substrate.

Abstract: Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxide buffer layer acts to improve capacitance and reduce capacitor leakage. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: An exemplary aspect of the present invention is an SRAM including: a first gate electrode that constitutes a first load transistor; a second gate electrode that extends in a longitudinal direction of the first gate electrode so as to be spaced apart from the first gate electrode, and constitutes a first drive transistor; a third gate electrode that extends in parallel to the first gate electrode, and constitutes a second load transistor; a first p-type diffusion region that is formed so as to intersect with the third gate electrode, and constitutes the second load transistor; and a first shared contact formed over the first and second gate electrodes and the first p-type diffusion region. The first p-type diffusion region extends to the vicinity of a first gap region between the first and second gate electrodes, and is not formed in the first gap region.

Abstract: A method for increasing an electrical resistance of a resistor that is within a semiconductor structure. A fraction of a surface layer of the resistor is oxidized with oxygen particles. In an embodiment, the fraction of the surface layer is heated by a beam of particles, such that the semiconductor structure is within a chamber that includes the oxygen particles as gaseous oxygen-comprising molecules. In an embodiment, the semiconductor structure is immersed in a chemical solution which includes the oxygen particles, wherein the oxygen particles includes oxygen-comprising liquid molecules, oxygen ions, or an oxygen-comprising gas dissolved in the chemical solution under pressurization. In an embodiment, the resistor is tested to determine whether the electrical resistance of the resistor after being oxidized with the oxygen particles is within a tolerance of a predetermined target resistance.

Abstract: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.

Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.

Abstract: A fluid flow machine has a main flow path, in which at least one row of blades (1) is arranged, and a shroud (2), which is embedded in a recess (3) of a component, with the component and the blades (1) being in relative rotational movement to each other. The assembly forming the shroud includes at least one internal chamber (7) which is suppliable with fluid from a source. The at least one internal chamber (7) is connected to the main flow path surrounding the blades (1) or to a cavity (9) surrounding the shroud (2) via at least one outlet (8) which is arranged on one side of the shroud (2). The shape of the outlet (8) and the shape of the outlet opening are such that a fluid barrier jet is generated at the outlet (8), which stops recirculation of fluid through the shroud cavity (9).

Abstract: An induction cookware comprising: a cooking body containing an inner pot inside, an insulation material disposed between the cooking body and the inner pot for maintaining the temperature of the inner pot. An induction coil is disposed in the bottom of the cooking body and with an extra magnetic field, the induction coil can generate AC current. The current flows through an electric heating tube connected to the bottom of the inner pot so as to heat the heating tube. Thereby, the heating tube directly transfer the heat to the inner pot for reducing the heat from transpiration. The structure of a cooking body with an inner pot inside can heat and slow cook the food inside the inner pot simultaneously, thus can add the delicious taste of the food and save the energy.

Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

Abstract: Methods for forming structures to use in atomic force probing of a conductive feature embedded in a dielectric layer and structures for use in atomic force probing. An insulator layer is formed on the dielectric layer such that the conductive feature is covered. A contact hole penetrates from a top surface of the insulator layer through the insulator layer to the conductive feature. The contact hole is at least partially filled with a conductive stud that is in electrical contact with the conductive feature and exposed at the top surface of the insulator layer so as to define a structure. A probe tip of an atomic force probe tool is landed on a portion of the structure and used to electrically characterize a device structure connected with the conductive feature.

Abstract: Problem to provide a container for an electromagnetic cooker which can be heated corresponding to impedance check frequency which differs depending on a manufacturer of an electromagnetic cooker or the like, can properly and easily set a heat generation characteristic, is excellent in marketability, configuration in use, disposability, handiness in cooking and the like, is suitable for retort foods, instant foods and the like, and exhibits high heating efficiency, means for resolution a container for an electromagnetic cooker includes a container body made of a non-conductive material and a conductive layer in a bottom portion of the container, wherein the ratio of resistance change (R?R0)/R0 of the conductive layer with respect to the impedance check frequency of a heating coil is set to 5.3 or more, and a ratio of inductance change (L?L0)/L0 of the conductive layer with respect to the impedance check frequency of the heating coil is set to ?0.17 or less. Here, R indicates the high-frequency resistance (.

Abstract: The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of at least one conductive path by cutting the chip, the position of the cutting line relative to the chip conditioning the identifier.

Abstract: Methods of forming a capacitor of an integrated circuit device include forming a lower electrode of the capacitor on an integrated circuit substrate without exposing a contact plug to be coupled to the lower electrode. A supporting conductor is formed coupling the lower electrode to the contact plug after forming the lower electrode. A capacitor dielectric layer is formed on the lower electrode and an upper electrode of the capacitor is formed on the capacitor dielectric layer.

Abstract: An example impeller includes: an impeller body in which an internal channel is formed, the internal channel extending inside the impeller body in a direction of a rotation axis spirally about the rotation axis to connect an inlet and an outlet; and at least one centrifugal vane provided in the impeller body. The internal channel including the inlet and the outlet has a predetermined passage diameter. An external channel is formed so as to continue to the outlet and go around the circumferential surface of the impeller body, the external channel being defined by the centrifugal vane and being recessed inward in the radial direction from the circumferential surface of the impeller body. At least a part in a flow direction of the external channel has a channel width in the direction of the rotation axis smaller than the width of the outlet.

Abstract: A method for manufacturing a micromachine is provided which can remove a sacrifice layer and can perform sealing without using a specific packaging technique. In a method for manufacturing a micromachine (1) including an oscillator (4), a step of forming a sacrifice layer around a movable portion of the oscillator (4); a step of covering a sacrifice layer with an overcoat film (8), followed by the formation of a penetrating hole (10) reaching the sacrifice layer in the overcoat layer (8); a step of performing sacrifice-layer etching for removing the sacrifice layer using the penetrating hole (10) in order to form a space around the movable portion; and a step of performing a film-formation treatment at a reduced pressure following the sacrifice-layer etching so as to seal the penetrating hole (10).

Abstract: An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26?). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26?), to inhibit the diffusion of dopant from the buried collector region (26?) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26?) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26?) can diffuse upward to meet the contact (33).

Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

Abstract: A stacked-chip packaging structure includes chip sets, a heat sink, a substrate, a circuit board, and solder balls. The chip sets are stacked together, each of which has a heat-dissipation structure and a chip. The heat-dissipation structure has a chip recess, through holes arranged in the chip recess, and an extending portion extending from the chip recess. The chip disposed in the chip recess has bumps. Each bump on the chip is correspondingly disposed in one of the through holes of the heat-dissipation structure. The extending portion of the heat-dissipation structure of each chip set contacts that of the neighboring chip set. The heat sink and the substrate are disposed at two opposite sides of the chip sets, respectively. The circuit board is below the substrate. The solder balls are between the circuit board and the substrate.

Abstract: A method for manufacturing a semiconductor device that comprises implanting a first dopant type in a well region of a substrate to form implanted sub-regions that are separated by non-implanted areas of the well region. The method also comprises forming an oxide layer over the well region, such that an oxide-converted first thickness of the implanted sub-regions is greater than an oxide-converted second thickness of the non-implanted areas. The method further comprises removing the oxide layer to form a topography feature on the well region. The topography feature comprises a surface pattern of higher and lower portions. The higher portions correspond to locations of the non-implanted areas and the lower portions correspond to the implanted sub-regions.

Abstract: A SiC semiconductor device having a MOS structure includes: a SiC substrate; a channel region providing a current path; first and second impurity regions on upstream and downstream sides of the current path, respectively; and a gate on the channel region through the gate insulating film. The channel region for flowing current between the first and second impurity regions is controlled by a voltage applied to the gate. An interface between the channel region and the gate insulating film has a hydrogen concentration equal to or greater than 4.7×1020 cm?3. The interface provides a channel surface having a (000-1)-orientation surface.