Abstract: A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. A layer of dielectric material is formed over the resistor protect layer. The dielectric material is masked and dry etched to leave a first portion of dielectric material over a first end of the thin film resistor and a second portion of dielectric material over a second end of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the dielectric material as a hard mask. Then a second dielectric layer is deposited and vias are etched down to the underlying portions of the resistor protect layer.

Abstract: Briefly, in accordance with an embodiment of the invention, a method to manufacture a phase change memory is provided. The method may include forming a first electrode contacting the sidewall surface and the bottom surface of the phase change material. The method may further include forming a second electrode contacting the top surface of the phase change material.

Abstract: The present invention provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming a silicon oxide masking layer over a substrate in a first active region and a second active region of a semiconductor device, patterning the silicon oxide masking layer to expose the substrate in the first active region. The method further includes forming a layer of dielectric material over the substrate in the first active region, the patterned silicon oxide masking layer protecting the substrate from the layer of dielectric material in the second active region.

Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.

Abstract: A hydrogen gas is supplied into a deposition chamber accommodating a silicon sputter target and a deposition target object, a high-frequency power is applied to said gas to generate plasma exhibiting H?/SiH* from 0.3 to 1.3 between an emission spectral intensity H? of hydrogen atom radicals at a wavelength of 656 nm and an emission spectral intensity SiH* of silane radicals at a wavelength of 414 nm in plasma emission, and chemical sputtering is effected on the silicon sputter target by the plasma to form a crystalline silicon thin film on the deposition target object. Thereafter a high-frequency power is applied to a terminally treating gas to generate plasma for terminating treatment and the surface of the crystalline silicon thin film is terminally treated by the plasma in the terminally treating chamber.

Abstract: Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a metal silicon compound deficient of silicon bonding atoms on a dielectric material overlying a semiconductor substrate conductively doped for PMOS and NMOS regions. The metal silicon compound overlying the NMOS region is converted to a metal silicon nitride and the metal silicon compound overlying the PMOS region is converted to a metal silicide. NMOS transistor gate electrodes comprising metal silicon nitride and PMOS transistor gate electrodes comprising metal silicide can be formed.

Abstract: A method of using a post-etch treatment system for removing photoresist and etch residue formed during an etching process is described. For example, the etch residue can include halogen containing material. The post-etch treatment system comprises a vacuum chamber, a radical generation system coupled to the vacuum chamber, a radical gas distribution system coupled to the radical generation system and configured to distribute reactive radicals above a substrate, and a high temperature pedestal coupled to the vacuum chamber and configured to support the substrate. The method comprises introducing a NxOy based process gas to the radical generation system.

Abstract: Methods for fabricating low contact resistance CMOS integrated circuits are provided. In accordance with an embodiment, a method for fabricating a CMOS integrated circuit including an NMOS transistor and a PMOS transistor disposed in and on a silicon-comprising substrate includes depositing a first silicide-forming metal on the NMOS and PMOS transistors. The first silicide-forming metal forms a silicide at a first temperature. At least a portion of the first silicide-forming metal is removed from the NMOS or PMOS transistor and a second silicide-forming metal is deposited. The second silicide-forming metal forms a silicide at a second temperature that is different from the first temperature. The first silicide-forming metal and the second silicide-forming metal are heated at a temperature that is no less than the higher of the first temperature and the second temperature.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor layer on a substrate. The first region of the substrate is expanded to push up the first portion of the semiconductor layer, thereby applying tensile stress to the first portion. The second region of the substrate is compressed to pull down the second portion of the semiconductor layer, thereby applying compressive stress to the second portion. An N type device is formed over the first portion of the semiconductor layer, and a P type device is formed over the second portion of the semiconductor layer.

Abstract: A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).

Abstract: In accordance with some embodiments, a ferroelectric polymer memory may be formed of a plurality of stacked layers. Each layer may be separated from the ensuing layer by a polyimide layer. The polyimide layer may provide reduced layer-to-layer coupling, and may improve planarization after the lower layer fabrication.

Abstract: A processing method for selectively reducing or removing the region to be exposed with energy ray in a film formed on a substrate, comprising relatively scanning a first exposure light whose shape on the substrate is smaller than the whole first region to be exposed against the whole first region to be exposed to selectively remove or reduce the first region to be exposed, and exposing a whole second region to be exposed inside the whole first region to be exposed with a second exposure light to selectively expose the whole second region to be exposed.

Abstract: A structure comprises a deep subcollector buried in a first region of a dual epitaxial layer and a reachthrough structure in contact with the deep subcollector to provide a low-resistive shunt which prevents CMOS latch-up for a first device. The structure may additionally include a near subcollector formed in a higher region than the deep subcollector and under another device. At least one reachthrough electrically connects the deep subcollector and the near subcollector. The method includes forming a merged triple well double epitaxy/double subcollector.

Abstract: A self-aligned split gate bitcell includes first and second regions of charge storage material separated by a gap devoid of charge storage material. Spacers are formed along sidewalls of sacrificial layer extending above and on opposite sides of the bitcell stack, wherein the spacers are separated from one another by at least a gap length. Etching the bitcell stack, selective to the spacers, forms a gap that splits the bitcell stack into first and second gates which together form the split gate bitcell stack. A storage portion of bitcell stack is also etched, wherein etching extends the gap and separates the corresponding layer into first and second separate regions, the extended gap being devoid of charge storage material. Dielectric material is deposited over the gap and etched back to expose a top surface of the sacrificial layer, which is thereafter removed to expose sidewalls of the split gate bitcell stack.

Abstract: A multi-layer PrxCa1-xMnO3 (PCMO) thin film capacitor and associated deposition method are provided for forming a bipolar switching thin film. The method comprises: forming a bottom electrode; depositing a nanocrystalline PCMO layer; depositing a polycrystalline PCMO layer; forming a multi-layer PCMO film with bipolar switching properties; and, forming top electrode overlying the PCMO film. If the polycrystalline layers are deposited overlying the nanocrystalline layers, a high resistance can be written with narrow pulse width, negative voltage pulses. The PCMO film can be reset to a low resistance using a narrow pulse width, positive amplitude pulse. Likewise, if the nanocrystalline layers are deposited overlying the polycrystalline layers, a high resistance can be written with narrow pulse width, positive voltage pulses, and reset to a low resistance using a narrow pulse width, negative amplitude pulse.

Abstract: The present invention supplies a manufacturing method of a semiconductor device, which includes a non-contact inspection process capable of confirming if a circuit or circuit element formed on an array substrate is normally performed and can decrease a manufacturing cost by eliminating wastes to keep a defective product forming. An electromotive force generated by electromagnetic induction is rectified and shaped by using primary coils formed on a check substrate and secondary coils formed on an array substrate, whereby a power source voltage and a driving signal are supplied to circuits or circuit elements on a TFT substrate so as to be driven.

Abstract: Method and apparatus for direct writing of passive structures having a tolerance of 5% or less in one or more physical, electrical, chemical, or optical properties. The present apparatus is capable of extended deposition times. The apparatus may be configured for unassisted operation and uses sensors and feedback loops to detect physical characteristics of the system to identify and maintain optimum process parameters.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor substrate including first and second well areas doped with second conductive ions, a third well area in the first well and doped with the second conductive ions, a base area in the third well and doped with first conductive ions, an emitter area in the third well and doped with the second conductive ions, an emitter electrode on the emitter area, a first contact plug in contact with the emitter electrode, a second contact plug in contact with the base area, a collector area in the second well and doped with the second conductive ions, and a third contact plug in contact with the collector area.

Abstract: A method for fabricating a cylindrical capacitor. The method includes forming an isolation structure including an interlayer on a substrate, the substrate having a plurality of contact plugs formed therein, forming a plurality of opening regions by etching the isolation structure, thereby exposing selected portions of the contact plugs, forming storage nodes on a surface of the opening regions, etching selected portions of the isolation structure to form a patterned interlayer that encompasses selected portions of the storage nodes, thereby supporting the storage nodes, removing remaining portions of the isolation structure, and removing the patterned interlayer to expose inner and outer walls of the storage nodes.

Abstract: Methods of forming LED packages and light emitting devices are provided. LED packages and light emitting devices are preferably formed from ceramic layers, such as AlN, though layers of non-ceramic materials can also be used. The layers are formed to include vias, apertures, and metallization layers. The layers are then bonded together to form a panel. The panel is scribed to form a grid of snap lines and then the panel is fractured along the snap lines. To form light emitting devices from the panel, LED dies are added and encapsulated before the panel is fractured.