Abstract: A method for forming a PECVD deposited amorphous carbon or ashable hard mask (AHM) in a trench or a via with less than 30% H content at a process temperature below 500° C., e.g., about 400° C. produces low H content hard masks with high selectivity and little or no hard mask on the sidewalls. The deposition method utilizes a pulsed precursor delivery with a plasma etch while the precursor flow is off.

Abstract: A seal assembly for a gas turbine is arranged in grooves of a rotor heat shield having several bends. The assembly comprises four seal portions overlapping one another and extending in the axial, radial, and circumferential direction with respect to the turbine rotor. A holding means retains the radial sections of one seal portion allowing a limited movement of said seal portion independent of another seal portion. The independent movement assures contact of the individual seal portions with all mating surfaces of the rotor heat shield and improved sealing function regardless of displacements of the rotor heat shield and tolerances of turbine parts.

Abstract: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.

Abstract: A fan shaft seat structure including a shaft bushing and a heat dissipation member. The shaft bushing has an open end, a closed end and a, connection section. A receiving space is defined between the open end and the closed end. The connection section extends from the closed end in a direction reverse to the receiving space. The heat dissipation member has a first face and a second face. The first face is flush with a first end of the connection section in contact with the closed end of the shaft bushing. The second face is flush with a second end of the connection section. The shaft bushing is integrally connected with the heat dissipation member to increase heat dissipation area and save working time and manufacturing cost as well as achieve better heat dissipation effect.

Abstract: The present invention is a production method for a semiconductor device equipped with a conductive film with predetermined film thickness on a sidewall of a concave portion formed in an insulating film, and comprises a step of forming the concave portion in the insulation film formed on a semiconductor substrate. Herein, the concave portion is a generic name of a via-hole and a trench. This production method comprises a step of forming a conductive film with film thickness, which is film thickness of a conductive film to be formed in the concave portion, and which is film thickness, calculated based upon the depth of the concave portion and a projected area of the sidewall of said concave portion when viewing the concave portion from the upper surface, and to be formed over the upper surface of the insulating film where the concave portion is formed. In other words, a film is formed taking the variation of configuration of these based upon a projected area of a via-hole or a trench into consideration.

Abstract: A method includes the steps of providing a carrier comprising a plurality of cavities; placing at least one semiconductor element into each of the cavities; filling the plurality of cavities with a packaging material; and removing the carrier.

Abstract: A single-bearing fan structure includes a fan frame having a bearing cup with a bearing received therein, the bearing cup having a radially inward protruded lip portion formed at a first end to abut on a top of the bearing, and a groove internally formed at a second end; a blade hub having a rotary shaft fixedly connected thereto with a distal end of the rotary shaft inserted into the bearing; a retainer engaged with the groove; a first elastic element fitted around the rotary shaft and located between the blade hub and the bearing; and a second elastic element received in the bearing cup and located between the bearing and the retainer. The first and second elastic elements and the bearing respectively axially and radially support the blade hub, enabling the fan structure to operate stably and have extended service life.

Abstract: Methods of manufacturing a semiconductor device having an RCAT are provided. The method includes forming a first recess having a first depth formed in an active region of a semiconductor substrate, and a second recess having a second depth that is less than the first depth formed in an isolation layer. The depth of the second recess is decreased by removing the isolation layer from the upper surface of the isolation layer by a desired thickness. A gate dielectric layer is formed on an inner wall of the first recess and a gate is formed on the gate dielectric layer.

Abstract: A computing system for implementing at least one electronic circuit with gain comprises at least one two-dimensional molecular switch array. The molecular switch array is formed by assembling two or more crossed planes of wires into a configuration of devices. Each device comprises a junction formed by a pair of crossed wires and at least one connector species that connects the pair of crossed wires in the junction. The junction has a functional dimension in nanometers, and includes a switching capability provided by both (1) one or more connector species and the pair of crossed wires and (2) a configurable nano-scale wire transistor having a first state that functions as a transistor and a second state that functions as a conducting semiconductor wire. Specific connections are made to interconnect the devices and connect the devices to two structures that provide high and low voltages.

Abstract: A high voltage BICMOS device and a method for manufacturing the same, which may improve the reliability of the device by securing a distance between adjacent DUF regions, are provided. The high voltage BICMOS device includes: a reverse diffusion under field (DUF) region formed by patterning a predetermined region of a semiconductor substrate; a diffusion under field (DUF) region formed in the substrate adjacent to the reverse DUF region; a spacer formed at a sidewall of the reverse DUF region; an epitaxial layer formed on an entire surface of the substrate; and a well region formed in contact with the DUF region.

Abstract: A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A sleeve insulator layer is deposited in an opening to protect one or more conductor layers from conductive contacts formed in the opening. The sleeve insulator layer electrically insulates a conductive plug from the conductor layer and self-aligns the BLCC so as to improve contact plug alignment tolerances between the BLCC and the capacitor or conductive components.

Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

Abstract: A LED packaging method includes a procedure of placing a screen plate having stepped holes on a substrate carrying LED chips, a procedure of reversing the screen plate with respect to the substrate, and a procedure of packaging the LED chips with a first packaging adhesive and a second packaging adhesive by means of applying the first packaging adhesive to the small diameter portion of each stepped hole when the first side of the screen plate is attached to the substrate and then applying the second packaging adhesive to the big diameter portion of each stepped hole after the screen plate is reversed.

Abstract: A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.

Abstract: The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of least one conductive path by cutting the chip, the position of the cutting line relative to the chip conditioning the identifier.

Abstract: A method of manufacturing a stacked-type semiconductor device, comprises: arranging a plurality of stacked chips obtained by stacking semiconductor chips on a plurality of stages on a support substrate; connecting a semiconductor chip of each stage in each stacked chip and the support substrate by wire while performing heating in units of stacked chips; performing plastic molding of each stacked chip; and separating the stacked chips from each other; an apparatus for manufacturing a stacked-type semiconductor device, comprising divided heater blocks formed under a support substrate on which a plurality of stacked chips obtained by stacking a plurality of semiconductor chips are arranged, the divided heater blocks being formed with respect to the stacked chips, and a heating device to selectively transmit heat to a stacked chip subjected to a wire bonding.

Abstract: First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.

Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.

Abstract: A method for making a semiconductor device with vertical electron injection, including: transferring a monocrystalline thin film onto a first face of a support substrate; producing at least one electronic component from the monocrystalline thin film; forming at least one recess in a second face of the substrate to enable electric or electronic access to the electronic component through the monocrystalline thin film; and producing a vertical electron injector configured to inject electrons into the electronic component.

Abstract: A film-forming method for forming a metal film on a substrate by a sputtering process includes the steps of depressurizing a processing space, in which deposition of the metal film is caused by the sputtering process, applying a DC bias voltage between the substrate and a target disposed in the processing space so as to face the substrate, and igniting plasma by introducing secondary electrons to the processing space from a secondary electron source.