Abstract: An integrated circuit includes a front-end interface, a back-end interface, a controller, and arbiter circuitry. The front-end interface communicates with a remote host over a front-end fabric. The back-end interface communicates with nonvolatile memory (NVM) subsystems over a back-end fabric. The controller is coupled between the front-end interface and the back-end interface. The controller receives commands from the remote host for the NVM subsystems, and stores the commands in queue pairs associated with the NVM subsystems. The arbiter circuitry receives data for the queue pairs, and selects a command from a first queue pair of the queue pairs based on a comparison of the data to one or more thresholds. The selected command is outputted to one or more of the NVM subsystems.

Abstract: An air freight rate data caching method and system. The method includes converting air freight rate data into a data format of a first-level cache, and storing same in the first-level cache; performing, on the basis of a flight origin city and a flight destination city, data fragmentation on the air freight rate data stored in the first-level cache so as to generate fragmented data; and storing the fragmented data, after same is validated, in a second-level cache. Each data node of the fragmented data cached in the second-level cache only includes part of the air freight rate data on which a fragmentation algorithm can be performed, and therefore, the horizontal expansion capacity of a cache system is improved relative to the case where cached data copies are all complete sets.

Abstract: A method of caching mapping table for use in a flash memory device having a flash memory controller and a flash memory is provided. The method includes: in response to a host read command, determining whether a group of a logical-to-physical (L2P) required by handling the host read command has been loaded to a DRAM of the flash memory controller; if the required group of the L2P mapping table has not been loaded to the DRAM, loading the required group of the L2P mapping table from the flash memory to a SRAM of the flash memory controller; directly accessing the SRAM to obtain an L2P address associated with the host read command from the required group of the L2P mapping table; and performing a read operation on the flash memory in response to the host read command according to the obtained L2P address.

Abstract: With a forever incremental snapshot configuration and a typical caching policy (e.g., least recently used), a storage appliance may evict stable data blocks of an older snapshot, perhaps unchanged data blocks of the snapshot baseline. If stable data blocks have been evicted, restore of a recent snapshot will suffer the time penalty of downloading the stable blocks for restoring the recent snapshot. Creating synthetic baseline snapshots and refreshing eviction data of stable data blocks can avoid eviction of stable data blocks and reduce the risk of violating a recovery time objective.

Abstract: Systems, methods, and apparatuses to implement spatially unique and location independent persistent memory encryption are described. In one embodiment, a system on a chip (SoC) includes at least one persistent range register to indicate a persistent range of memory, an address modifying circuit to check if an address for a memory store request is within the persistent range indicated by the at least one persistent range register, and append a unique identifier value, for a component corresponding to the memory store request for the address, to the address to generate a modified address and output the modified address as an output address when the address is within the persistent range, and output the address as the output address when the address is not within the persistent range, and an encryption engine circuit to generate a ciphertext based on the output address.

Abstract: The present disclosure provides methods, systems, and non-transitory computer readable media for managing a primary storage unit of an accelerator. The methods include assessing activity of the accelerator; assigning, based on the assessed activity of the accelerator, a lease to a group of one or more pages of data on the primary storage unit, wherein the assigned lease indicates a lease duration; and marking, in response to the expiration of the lease duration indicated by the lease, the group of one or more pages of data as an eviction candidate.

Abstract: A communication method applied to a computer system that includes a first subsystem and a second subsystem. A safety level of the first subsystem is higher than a safety level of the second subsystem. The first subsystem includes a memory access checker. The method includes the memory access checker receives a memory access request from a memory access initiator, determines, based on preconfigured memory safety level division information, whether a safety level of a memory to be accessed by the memory access initiator matches a safety level of the memory access initiator, and allows the memory access initiator to access the memory address when the safety level of the memory matches the safety level of the memory access initiator.

Abstract: A method of operating a storage device includes storing received input data of a first format, converting the input data into a second format for an operation to be performed on the input data of the second format using an operator included in the storage device, and converting the input data into a second format for an operation to be performed on the input data, through an operator included in the storage device, and re-storing the input data of the second format.

Abstract: A system is disclosed. The system may include a processor and a memory coupled to the processor. A storage device may also be coupled to the processor. The storage device may include a first interface and a second interface. The storage device may be configured to extend the memory. A mode switch may select a selected interface of the first interface and the second interface for a command issued by the processor.

Abstract: A content addressable memory circuit is provided that includes: multiple integrated circuit memory devices that include memory address locations that share common memory addresses; buffer circuits operatively coupled to the memory devices; a hash table that includes a plurality of hash values that each corresponds to one or more key values; one or more processor circuits configured with instructions to perform operations that include: assigning each hash value to a memory address location based upon a first portion of the hash value; storing each key value at a memory address location assigned to a first portion of a hash value that corresponds to the key value; copying a first key value from a first memory address location within a memory device to a buffer circuit operatively coupled to the memory device; copying the first key value from the buffer circuit operatively coupled to the memory device to a second memory address location of the memory device; and assigning a second portion of a hash value that co

Abstract: Examples describe memory refresh operations for memory subsystems. One example is a method for a memory controller, the method including entering a first state upon exiting self-refresh state, wherein the first state comprises activating a first timer. The method includes entering a second state from the first state upon detecting an end of an active period and detecting that the first timer has not expired. The method includes entering a third state from the second state upon detecting expiration of the second state, wherein the third state comprises re-entering the self-refresh state.

Abstract: A method for caching content, a method for reading content, a client, and a storage medium are provided. The method for caching content includes: acquiring JSON data corresponding to content to be delivered, and determining identification information corresponding to the JSON data; grouping the JSON data and storing the grouped JSON data according to the identification information to obtain a memory list corresponding to the identification information, and writing the JSON data to a target disk according to the identification information and the memory list; performing video preloading processing on the content to be delivered according to the JSON data to obtain preloaded video data, and determining address information corresponding to the preloaded video data; and storing the address information in the memory list and the target disk according to the identification information, to complete caching of the JSON data and the preloaded video data.

Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

Abstract: An apparatus comprises at least one processing device comprising a processor coupled to a memory and a drive bay enclosure of a storage system comprising a housing with one or more drive bays, the housing of the drive bay enclosure comprising one or more status indicators proximate an opening for at least a given one of the one or more drive bays. The at least one processing device is configured to perform steps of determining status information for the given drive bay, and controlling the one or more status indicators proximate the opening for the given drive bay based at least in part on the determined status information.

Abstract: Systems and methods for providing object versioning in a storage system may support the logical deletion of stored objects. In response to a delete operation specifying both a user key and a version identifier, the storage system may permanently delete the specified version of an object having the specified key. In response to a delete operation specifying a user key, but not a version identifier, the storage system may create a delete marker object that does not contain object data, and may generate a new version identifier for the delete marker. The delete marker may be stored as the latest object version of the user key, and may be addressable in the storage system using a composite key comprising the user key and the new version identifier. Subsequent attempts to retrieve the user key without specifying a version identifier may return an error, although the object was not actually deleted.

Abstract: A method for managing a memory system may include monitoring one or more accesses of a page of memory, determining, based on the monitoring, an access pattern of the page of memory, and selecting, based on the access pattern, a coherency bias for the page of memory. The monitoring may include maintaining an indication of the one or more accesses. The determining may include comparing the indication to a threshold. Maintaining the indication may include changing the indication in a first manner based on an access of the page of memory by a first apparatus. Maintaining the indication may include changing the indication in a second manner based on an access of the page of memory by a second apparatus. The first manner may counteract the second manner.

Abstract: When load requests are generated to support data processing operations, the load requests are buffered in pending load buffer circuitry prior to being carried out. Coalescing circuitry determines for a first load request whether a set of one or more subsequent load requests buffered in the pending load buffer circuitry satisfies an address proximity condition. The address proximity condition is satisfied when all data items identified by the set of one or more subsequent load requests are comprised within a series of data items which will be retrieved from the memory system in response to the first load request. When the address proximity condition is satisfied, forwarding of the set of one or more subsequent load requests is suppressed.

Abstract: A memory controller includes a first buffer configured to receive a first memory request from a host and store the first memory request, a request scheduler configured to determine an order in which the first memory request is transferred to a command generator, a request generator configured to generate one or more second memory requests based on a generation parameter of the first memory request, in response to an address of the first memory request corresponding to a processing in memory (PIM) memory, the command generator configured to generate a first command corresponding to the first memory request and one or more second commands corresponding to the one or more second memory requests, and store the generated first command and the one or more second commands in a second buffer, and a command scheduler configured to schedule the first command and the one or more second commands.

Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a common substrate and a first integrated circuit (IC) chip disposed on the common substrate. The first IC chip includes a first memory interface. A second IC chip is disposed on the common substrate and includes a second memory interface. A first memory device is disposed on the common substrate and includes memory and a first port coupled to the memory. The first port is configured for communicating with the first memory interface of the first IC chip. A second port is coupled to the memory and communicates with the second memory interface of the second IC chip. In-memory processing circuitry is coupled to the memory and controls transactions between the first memory device and the first and second IC chips.

Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a no-locality hint vector memory access instruction. The no-locality hint vector memory access instruction to indicate a packed data register of the plurality of packed data registers that is to have a source packed memory indices. The source packed memory indices to have a plurality of memory indices. The no-locality hint vector memory access instruction is to provide a no-locality hint to the processor for data elements that are to be accessed with the memory indices. The processor also includes an execution unit coupled with the decode unit and the plurality of packed data registers. The execution unit, in response to the no-locality hint vector memory access instruction, is to access the data elements at memory locations that are based on the memory indices.