Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.

Abstract: An apparatus including a plurality of set arbitration circuits and a die arbitration circuit. The set arbitration circuits may each be configured to receive first commands and second commands and comprise a bank circuit configured to queue bank data in response to client requests and a set arbitration logic configured to queue the second commands in response to the bank data. The die arbitration circuit may be configured to receive the commands from the set arbitration circuits and comprise a die-bank circuit configured to queue die data in response to the client requests and a die arbitration logic configured to queue the second commands in response to the die data. Queuing the bank data and the die data for the second commands may maintain an order of the client requests and prioritize the first commands corresponding to a current controller over the first commands corresponding to a non-current controller.

Abstract: A processing-in-memory (PIM) system includes a PIM device and a controller. The PIM device includes a data storage region and an arithmetic circuit for performing an arithmetic operation for data outputted from the data storage region. The controller is configured to control the PIM device. The PIM device is configured to transmit arithmetic quantity data of the arithmetic circuit to the controller in response to a request of the controller.

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.

Abstract: This application provides a data reading method for a retrieval task and a retrieval apparatus. The method includes receiving a first retrieval task request, where the first retrieval task request corresponds to a first retrieval start address and a first retrieval end address in a target data area, and reading data for a first retrieval task starting from the first retrieval start address. The method includes receiving a second retrieval task request in a process of reading data for the first retrieval task. The method further includes obtaining an address of data to be read for the first retrieval task after receiving the second retrieval task request, and determining a second retrieval start address of a second retrieval task in the target data area based on the address of the data to be read. The method further includes reading data for the second retrieval task starting from the second retrieval start address.

Abstract: Processing circuitry processes instructions in one of at least three domains each associated with a corresponding physical address space, and issues a memory access request to a memory system, the memory access request comprising a partition identifier (selected based on programmable partition identifier selection information associated with a current software execution environment which caused the memory access request to be issued) and a multi-bit partition identifier space indicator indicating a selected partition identifier space (selected from among at least three partition identifier spaces based on a current domain of the processing circuitry).

Abstract: Techniques performed by a computing device of storing data in a data storage system are provided. A method includes (a) storing references to write commands within entries of a first chained hash table (CHT), the first CHT being pointed to by a first data structure representative of a logical disk; (b) keeping track of a load factor of the first CHT during operation; and (c) in response to determining that the load factor of the first CHT has transitioned outside of predetermined bounds: (1) creating a second CHT and a second data structure representative of the logical disk, the second CHT being pointed to by the second data structure; (2) linking the second data structure to the first data structure via a linked list; and (3) storing references to new write commands directed at the logical disk within entries of the second CHT rather than the first CHT.

Abstract: A method and apparatus for cache management and eviction polices using unsupervised reinforcement learning schemes is disclosed.

Abstract: Operation of a non-volatile memory (NVM) storage module may comprise receiving a plurality of commands as associated with a plurality of priority-based queues from a host-memory. A received command is evaluated in accordance with a priority associated with the queue storing the command and a size of the command. The evaluated command is split into a plurality of sub-commands, each of the sub-commands having a size determined in accordance with the evaluation. A predetermined number of hardware resources are allocated for each of the evaluated command based on at least the size of each of the sub-commands to thereby enable a processing of the evaluated command based on the allocated resources. Quality of service (QoS) for the evaluated-command may thus be augmented.

Abstract: Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.

Abstract: A method for performing verification and testing of a device under test (DUT) is described. The method includes receiving, by a processing device, inputs from a user regarding a hardware design for the DUT. The processing device presents cover group attribute suggestions to the user based on the hardware design and receives cover group information from the user corresponding to one or more cover group attributes of one or more cover groups based on the cover group attribute suggestions. Based on the cover group information, the processing device automatically generates verification code, including one or more cover group definitions.

Abstract: A data storage device includes a shared command queue, a queue controller, a processor, and a memory. The command queue is configured to queue a plurality of jobs transmitted from a plurality of host processors. The queue controller is configured to classify the plurality of jobs into a plurality of levels of jobs according to priority threshold values and assign jobs of the plurality of levels of jobs the processor. The processor is configured to process the jobs assigned by the queue controller. The memory may store data needed to process the job.

Abstract: A node controller is provided to include a first interface to interface with one or more processors, a second interface including a plurality of ports to interface with node controllers within a base node and other nodes in the cache-coherent interconnect network. The node controller can further include a third interface to interface with a first plurality of memory devices and a cache coherence management logic. The cache coherence management logic can maintain, based on a first circuitry, hardware-managed cache coherency in the cache-coherent interconnect network. The cache coherence management logic can further facilitate, based on a second circuitry, software-managed cache coherency in the cache-coherent interconnect network.

Abstract: A memory device including an interface circuit for data conversion according to different endian formats includes an interface circuit that performs data conversion with hardware in a data transfer path inside the memory device in accordance with a memory bank, a processing element (PE), and an endian format of a host device. The interface circuit is (i) between a memory physical layer interface (PHY) region and a serializer/deserializer (SERDES) region, (ii) between the SERDES region and the memory bank or the PE, (iii) between the SERDES region and a bank group input/output line coupled to a bank group including a number of memory banks, and (iv) between the PE and bank local input/output lines coupled to the memory bank.

Abstract: A memory system includes a memory device including memory banks and a data bus management circuit and a host coupled to the memory device. The host includes a memory controller detecting at least one trigger initiated by at least one application for performing at least one operation on data stored within the memory device, the at least one operation including at least one of a data copy operation, and a data processing operation, and performing the at least one operation on the data within the memory device by enabling movement of the data between the data bus management circuit of the memory device and at least one memory bank of the memory banks, without exchanging the data with the host, using at least one buffer fill command and at least one buffer copy command.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a parent physical function (PF), receive one or more child PFs, determine whether any part of a first child command of a first child PF of the one or more child PFs can be executed prior to receiving approval from the parent PF, and start executing the first child command. The controller is further configured to initialize an indirect queue, set fetching pointers of the indirect queue to the first child command, mimic a doorbell for the first child command, fetch the first child command, determine whether the first child command has started execution by a child PF flow, and complete the first child command.

Abstract: A solid state drive (SSD) includes a first storage region classified as byte addressable NV storage region and a controller communicatively coupled to the first storage region by a bus. The controller detects a reduced storage capacity of the first storage region, and in response to the detection, reclassifies the first storage region as a block addressable NV storage region. The SSD dynamically changes byte addressable NV storage regions to block addressable NV storage regions as the byte addressable NV storage regions are degraded, thereby extending the longevity of the SSD.

Abstract: A method of operating a storage means, wherein for writing and storing a storage item to the storage means the storage item to be written and stored—in particular by using the concept and theory of identification—is provided, a encoding process by means of randomization is applied to the storage item to generate and to provide a randomized encoded storage item, and the randomized encoded storage item is written and stored to the storage means. At least a first randomization process is underlying the encoding process and is a randomization process dedicated and assigned to the underlying storage means. The present disclosure further refers to a unit for operating a storage means, to a storage means and to a system for processing data. By having two randomization processes underlying the encoding process, a distinction can be made between a secrecy insuring and secrecy non-ensuring randomization processes.

Abstract: A storage device includes a non-volatile memory including a plurality of non-volatile memory cells, a buffer memory configured to temporarily store write data to be written to the non-volatile memory or read data read from the non-volatile memory, and a controller configured to receive a sleep mode signal from an external host. When the sleep mode signal is received by the controller, the controller is configured to block a first power supplied to the non-volatile memory and set the buffer memory to one of a first mode in which a second power is blocked from being supplied to the buffer memory and a second mode in which the buffer memory operates with low power. The write data stored in the buffer memory is written to the non-volatile memory when the buffer memory is set to the first mode.

Abstract: A method and apparatus for controlling access to memory is disclosed. In one implementation, a memory controller may receive a memory access request that may include a virtual memory address, a device identifier (ID) and a protected access indicator. Additionally, the memory controller can receive page table entries including a physical memory address based on the virtual memory address and a security attribute associated with the physical memory address. The memory controller may access a memory based on the physical memory address, the security attribute, the protected access indicator, and the device ID.