Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to program a first block in a first die of the memory device and a second block in a second die of the memory device, wherein the first die and the second die are assigned to a die group; and associate the die group with a threshold voltage offset bin.

Abstract: Systems, methods and apparatus to implement bipolar read retry. In response to a determination that a first result of reading a set of memory cells using a first magnitude of read voltage is erroneous, a second magnitude of read voltage, greater than the first magnitude, is identified for the bipolar read retry. In the retry, a controller uses voltage drivers to apply, to the set of memory cells, first voltages of the second magnitude in a first polarity to obtain a second result of reading the set of memory cells and, after the second result is generated and in parallel with decoding the second result, apply second voltages of the second magnitude in a second polarity, opposite to the first polarity.

Abstract: A memory device includes a local input/output circuit and a main input/output circuit. The local input/output circuit is configured to generate a first local write signal based on a first global write signal and a second global write signal, and configured to transmit the first local write signal to a plurality of first bit lines. The main input/output circuit include a first latch and logic elements. The first latch is configured to generate a first bit write mask signal based on a clock signal. The logic elements are configured to generate the first global write signal and the second global write signal based on the clock signal and the first bit write mask signal.

Abstract: A method of authenticating a speech signal in a first device comprises receiving a speech signal, and performing a live speech detection process to determine whether the received signal represents live speech. The live speech detection process generates a live speech detection output. A certificate is formed by encrypting at least the live speech detection output. The received signal, and the certificate, are transmitted to a separate second device.

Abstract: An oxide semiconductor-based FRAM is provided in the present invention, including a substrate, a word line on the substrate, a gate insulating layer on the word line, an oxide semiconductor layer on the gate insulating layer, a source and a drain respectively on the oxide semiconductor layer and spaced apart at a distance, wherein the source and the drain further connect respectively to a plate line and a bit line, a ferroelectric dielectric layer on the source, the drain and the oxide semiconductor layer, and a write electrode on the ferroelectric dielectric layer, wherein the write electrode, the ferroelectric dielectric layer, the oxide semiconductor layer, the gate insulating layer and the word line overlap each other in a direction vertical to the substrate.

Abstract: Disclosed in some examples are methods, systems, and machine readable mediums for applications that detect indicators of data exfiltration through applications such as browser-based interfaces. The disclosed system monitors file system element events related to one or more target applications (such as browsers) through operating system interfaces. Once an event of interest is detected, the system interfaces with the browser to determine a context for the event of interest that may include a URL of a website that the user was visiting corresponding to the file system element event. If the URL is directed towards a prohibited site, a notification may be generated that may be used as a signal to alert an administrator. As used herein, a file system element may include a file, directory, folder, archive, blob, raw storage, metadata, or the like File system element events may include copying, deleting, modifying, or moving a file system element.

Abstract: A method for microphone management is provided. The method includes receiving an enable secure audio indicator. In response to receiving the enable secure audio indicator, a set of computing devices are identified, and a communication is initiated to each device in the set of computing devices. The communication includes an instruction to disable a microphone associated with each respective device.

Abstract: Systems, methods, and computer-readable media are disclosed for systems and methods for sending and receiving requests to delete and/or retrieve certain data. Example methods may include sending from an electronic device a request to delete and/or retrieve selected data from a server based on selected categories, receiving the request at the server, and determining data to delete and/or retrieve on the server based on the request from the electronic device, deleting and/or retrieving the data on the server, and/or sending the retrieved selected to the electronic device.

Abstract: A kiosk device is shared by many users of an organization in a sequential manner. The kiosk is provisioned so that each of the appropriate users of the organization may use it, and so that each such user may be provided with a federated identity by an external identity provider (IdP) system. The federated identity may be used to automatically provide the user with access to the user's different resources (e.g., the user's accounts on various third-party applications). An authenticator component of the kiosk device communicates with the external IdP system so as to securely and transparently provide the users with a federated identity. In order to provide additional security, the authenticator component and/or the IdP system may take into account organization-specific details when authenticating a user, such as whether a particular user is expected to be on duty with the organization at the current time.

Abstract: SRAM arrays are provided. A SRAM array includes a plurality of SRAM cells and a plurality of well strap cells. Each of the SRAM cells arranged in the same column of the cell array includes a first transistor formed in a first P-type well region of a substrate, a second transistor formed in an N-type well region of the substrate, and a third transistor formed in a second P-type well region of the substrate. Each well strap cell is arranged on one of the columns in the cell array and includes a first P-well strap structure formed on the first P-type well region, a second P-well strap structure formed on the second P-type well region, and an N-well strap structure formed on the N-type well region. The first and second P-well strap structures and the N-well strap structure are separated from the SRAM cells by a dummy area.

Abstract: The present disclosure includes systems, apparatuses, and methods for improving safety and correctness of data reading in flash memory devices associated with System-on-Chips. An example may include a plurality of sub-arrays, a plurality of memory blocks in each sub-array of the plurality of sub-arrays, a plurality of memory rows in each memory block of the plurality of memory blocks, and a plurality of extended pages in each memory row of the plurality of memory rows, wherein each extended page of the plurality of extended pages includes a group of data, an address, and an error correction code (ECC).

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of groups, each including a plurality of memory cells. The memory controller is configured to determine whether to execute a refresh process for a first group based on whether a first temperature in a write process for the first group and a second temperature after the write process for the first group satisfy a first condition.

Abstract: According to an embodiment, a semiconductor device includes a control circuit. The control circuit is configured to receive a first command and execute, based on the first command, a first operation and a second operation. The second operation is executed after the first operation. The control circuit is further configured to output a first signal from a start of the first operation to a start of the second operation. The first signal indicates that the semiconductor device is in a busy state in which the semiconductor device refrains from accepting, from an external controller, a second command for execution of the first operation and a third command for execution of the second operation.

Abstract: A semiconductor memory device includes a plurality of planes defined in a plurality of chip regions; and a rescue circuit configured to disable a failed plane and enable a normal plane from among the plurality of planes, wherein the semiconductor memory device operates with only normal planes that are enabled.

Abstract: Systems and method are provided for data self-protection. The systems and methods may involve installing a sentry on a computer system, the sentry including a file system filter installed on a kernel of that computer system; providing a central sentry platform in communication with the sentry, operating the central sentry platform to send a data self-protection policy to the sentry, the data self-protection policy being encrypted so that it can only be modified by the central sentry platform; operating the file system filter to control access to encrypted data stored on the computer system, by, for each process making a file access request to the encrypted data, the file system filter receiving and handling that file access request according to the data self-protection policy; and, operating the central sentry platform to monitor the sentry and to receive information from the sentry regarding access to the encrypted data.

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

Abstract: Provided are an apparatus, a memory device, and a method for storing a plurality of parameter codes for an operation parameter. The memory device includes a mode register and a control logic circuit. To set a first operating condition and a second operating condition for one operation parameter, the mode register stores a first parameter code for the operation parameter and a second parameter code, which is expressed as an offset value from the first parameter code. The control logic circuit sets the first operating condition as a current operating condition of the memory device by using the first parameter code based on a first control code and sets the second operating condition as the current operating condition of the memory device by using the first parameter code and the second parameter code based on a second control code.

Abstract: In accordance with a first aspect of the present disclosure, a method is conceived for setting permissions for cryptographic keys in a cryptographic processing system, comprising: generating at least one cryptographic key to be protected; assigning one or more configurable properties to said cryptographic key; wherein the configurable properties define at least one of a permission of performing a first set of predefined operations on the cryptographic key and a permission of using the cryptographic key for performing a second set of predefined operations. In accordance with a second aspect of the present disclosure, a corresponding computer program is provided. In accordance with a third aspect of the present disclosure, a corresponding cryptographic processing system is provided.

Abstract: In some embodiments, a method may be performed by a computing device that involves displaying an identifier indicative of a file, the display of the identifier being readable by a second device, receiving first data from the second device in response to the identifier being read by the second device, and enabling performance of at least one action with respect to the file with use of the first data. In some embodiments, the method may further involve receiving a first encryption fragment associated with the file, receiving, from the second device, a second encryption fragment associated with the file, reconstructing, using at least the first encryption fragment and the second encryption fragment, an encryption key enabling viewing of the file, and viewing the file using the encryption key.