Abstract: A system includes at least one processor to receive training data and generate at least one machine learning rule based on the training data to apply when a condition occurs, continually monitor at least one resource associated with a computing network for the condition in the computing network that may trigger an authorization control modification, the condition comprising one of an active project that uses the at least one resource, a security alert level change, a resource locality change, metadata associated with the condition, a skill assessment, and a business state analysis, determine that the condition has occurred in the computing network, and dynamically and automatically modify a user authorization control for at least one particular user responsive to the machine learning rule.

Abstract: Timed-based credential access to computer networks, applications and/or data files. A multi-factor authentication process in which time is an intrinsic part of the authentication/log-in process. Time periods are defined that coincide with a user's expected periods of use, such as standard work hours, and the user's credentials are only valid during the defined time period. This means that the user can only gain access to the computer network and/or the secure application(s) or data file(s) during those defined time periods. As a result, nefarious actors, in wrongful possession of a user's credentials, that attempt to access the computer network, application and/or data file outside of the defined period of time will be prevented from doing so.

Abstract: Methods and systems for using a challenge-response problem to deter malicious clients are described. A denial of a first login request for logging into an account by a computing device is detected. A second login request for logging into the account is received from the computing device. A reputation score for the second login request is determined based on the denial of the first login request. A number of terms for a challenge-response problem is set based on the determined reputation score. The challenge-response problem is configured to use the set number of terms and sent to the computing device. The second login request is authorized in response to verifying a second login credential and a solution to the challenge-response problem received from the computing device.

Abstract: Methods and systems for building security applications can be provided. Data policies for accessing security data can be set, and a module pipeline including one or more modules selected from a plurality of modules can be generated. The modules can include at least one module operable to apply a predictive security application or model for detection or identification of security threats. Module execution policies governing execution of the one or more modules in the module pipeline also can be set. Upon receipt of a request to initiate execution of the module pipeline, it can be determined if the execution thereof would violate the data policies or the module execution policies. If so, execution of the module pipeline can be blocked, otherwise the module pipeline can be executed to process the portion of the security data.

Abstract: The present technology pertains to a organization directory hosted by a synchronized content management system. The corporate directory can provide access to user accounts for all members of the organization to all content items in the organization directory on the respective file systems of the members' client devices. Members can reach any content item at the same path as other members relative to the organization directory root on their respective client device. In some embodiments novel access permissions are granted to maintain path consistency.

Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with sharing data with a particular audience are described. Examples can include receiving first data at a processing resource, determining whether the first data comprises a combination of bits associated with text or an image, or both, and comparing the combination of bits to second data stored on a memory resource. Examples can include identifying one or more words or one or more images represented by the first data, or both, based on the comparison and assigning to the first data first metadata representative of a first security categorization and a first confidence level and second metadata representative of a second security categorization and a second confidence level Examples can include transmitting an output that comprises the first data or third data that comprises a modified combination of bits relative to the combination of bits of the first data.

Abstract: Systems and methods are provided for compliance management across multiple cloud environments. In some embodiments, the method includes receiving a rule, the rule using one or more statelets, wherein at least one of the statelets represents information procurable from a second cloud environment, wherein the second cloud environment is external to the first cloud environment; procuring the information from the second cloud environment; and executing the rule within the first cloud environment.

Abstract: A device within a small cell may establish a first secure communication channel between the device and a network device based on a first type of encryption. The device within the small cell may transmit data between the small cell and a core network via the first secure communication channel. The device within the small cell may receive information associated with a second type of encryption, wherein the second type of encryption is different from the first type of encryption. The device within the small cell may terminate the first secure communication channel. The device within the small cell may establish a second secure communication channel between the device and the network device based on the information associated with the second type of encryption. The device within the small cell may transmit further data between the small cell and the core network via the second secure communication channel.

Abstract: An IC structure includes a bit line extending in a first direction, first and second pluralities of FinFETs, and a plurality of eFuses. The FinFETs of the first plurality of FinFETs alternate with the FinFETs of the second plurality of FinFETs along the bit line, each eFuse of the plurality of eFuses includes a conductive segment extending between first and second contact regions, the first contact region is electrically connected to the bit line, and the second contact region is electrically connected to each of an adjacent FinFET of the first plurality of FinFETs and an adjacent FinFET of the second plurality of FinFETs.

Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.

Abstract: A system includes a memory device to maintain data for a machine learning operation. The memory device includes solder balls. The system further includes a machine learning processing device to perform the machine learning operation. The system further includes a processing device to select, based on the machine learning operation, a set of solder balls from the plurality of solder balls to transmit the data from the non-volatile memory device to the machine learning processing device.

Abstract: An oxide semiconductor based FRAM is provided in the present invention, including a substrate, a write electrode on the substrate, a ferroelectric dielectric layer on the write electrode, an oxide semiconductor layer on the ferroelectric dielectric layer, a source and a drain respectively on the oxide semiconductor layer and spaced apart at a distance, wherein the source and the drain are further connected to a plate line and a bit line respectively, a gate insulating layer on the source, the drain and the oxide semiconductor layer, and a word line on the gate insulating layer, wherein the word line, the oxide semiconductor layer, the ferroelectric dielectric layer and the write electrode overlapping each other in a direction vertical to the substrate.

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: Methods, systems, and devices for reducing duty cycle degradation for a signal path are described. In some examples, a memory system may alternate a polarity of a signal line or signal path that includes a set of transistors during successive active periods of the memory system. In some cases, the memory device may include an inversion control component configured to operate the signal using either a first polarity or a second polarity. The inversion control component may receive an indication when the memory system enters an active period, and may accordingly alternate or the polarity of the signal path during successive active periods. In some examples, the signal path may be coupled with one or more output components which may uninvert signals from the signal path when the inversion control component has inverted the polarity of the signal path.

Abstract: Embodiments of the disclosure are drawn to apparatuses methods for checking redundancy information for row addresses prior to performing various refresh operations, such as auto refresh and targeted refresh operations. In some examples, refresh operations may be multi pump refresh operations. In some examples, a targeted refresh operation may be performed prior to an auto refresh operation responsive to a multi pump refresh operation. In some examples, redundancy information for the auto refresh operation may be performed, at least in part, during the targeted refresh operation. In some examples, refresh operations on word lines may be skipped when the redundancy information indicates the word line is defective or unused.

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W? values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)?(W?). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W? values.

Abstract: In a method of testing a nonvolatile memory device including a first semiconductor layer in which and a second semiconductor layer is formed prior to the first semiconductor layer, circuit elements including a page buffer circuit are provided in the second semiconductor layer, an on state of nonvolatile memory cells which are not connected to the page buffer circuit is mimicked by providing a conducting path between an internal node of a bit-line connection circuit connected between a sensing node and a bit-line node of the page buffer circuit and a voltage terminal to receive a first voltage, a sensing and latching operation with the on state being mimicked is performed in the page buffer circuit and a determination is made as to whether the page buffer circuit operates normally is made based on a result of the sensing and latching operation.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: A memory includes a first deck including a first set of word lines, a second deck above the first deck and including a second set of word lines, and a controller. The controller is configured to apply a program voltage to a first target word line of the first set of word lines in the first deck, and apply a first pass voltage to at least one of the first set of word lines that is below the first target word line when applying the program voltage to the first target word line. The controller is also configured to apply the program voltage to a second target word line of the second set of word lines in the second deck, and apply a second pass voltage to at least one of the second set of word lines that is below the second target word line when applying the program voltage to the second target word line. The second pass voltage is greater than the first pass voltage.

Abstract: Analyzing and reporting anomalous internet traffic data by accepting a request for a connection to a virtual security appliance, collecting attribute data about the connection, applying an alert module to the data, and automatically generating an alert concerning an identified incident. An alert system for analyzing and reporting the anomalous internet traffic data. A processor to analyze and report anomalous internet traffic data.