Patents Examined by Henry Choe
  • Patent number: 11742806
    Abstract: The present disclosure provides a Multiple Inputs Multiple Outputs RF front-end amplifier circuit, chip, and electronic device and a method for configuring signal path. The RF front-end amplifier circuit includes: at least two low-noise amplifying modules, each of which amplifies one voltage signal and converts into one or more intermediate current signals; a voltage output module, connected to each of the low-noise amplifying modules, for combining the intermediate current signal output by the low-noise amplifying module and converting them into one or more output voltage signals. The RF front-end amplifier circuit can be applied to an RF front-end with a Multiple Inputs Multiple Outputs structure.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: August 29, 2023
    Assignee: Montage LZ Technologies (Shanghai) Co., Ltd.
    Inventors: Jun Xu, Shunfang Wu, Shawn Si
  • Patent number: 11742805
    Abstract: The present disclosure provides a multiple output low noise amplifier circuit, chip and electronic device. The multiple output low noise amplifier circuit includes: a first processing module for amplifying an input voltage signal and converting it into at least two first current signals; a second processing module for impedance matching at the input terminal of the low noise amplifier circuit, and for amplifying the input voltage signal and converting it into at least two second current signals; a voltage output module, connected to the first processing module and the second processing module, for combining the first current signals and the second current signals and converting them into output voltage signals. The low noise amplifier circuit can convert a single input voltage signal to at least two output voltage signals, and is applicable in RF front ends with multiple output terminals.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: August 29, 2023
    Assignee: Montage LZ Technologies (Shanghai) Co., Ltd.
    Inventors: Jun Xu, Shunfang Wu, Shawn Si
  • Patent number: 11742807
    Abstract: Disclosed is a dual-band coupling low-noise amplifying circuit and an amplifier, which comprises an input frequency dividing circuit, a high-frequency amplifying circuit, a low-frequency amplifying circuit and an output combining circuit. The input frequency dividing circuit includes a first duplexer, a first capacitor and a second capacitor, and the output combining circuit includes a second duplexer, a third capacitor and a fourth capacitor. The input frequency dividing circuit divides the received radio frequency signals into high-frequency signals and low-frequency signals, then inputs the high-frequency signals into the high-frequency amplifying circuit for power amplification, and inputs the low-frequency signals into the low-frequency amplifying circuit for power amplification, and outputs the high-frequency signals and the low-frequency signals after power amplification through the output combining circuit.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: August 29, 2023
    Assignee: GUANGDONG UNIVERSITY OF TECHNOLOGY
    Inventors: Zhihao Zhang, Jinfeng Chen, Xinlei Yang, Guohao Zhang
  • Patent number: 11742802
    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: August 29, 2023
    Assignee: pSemi Corporation
    Inventors: Poojan Wagh, Kashish Pal, Robert Mark Englekirk, Tero Tapio Ranta, Keith Bargroff, Simon Edward Willard
  • Patent number: 11736072
    Abstract: Herein disclosed in some embodiments is a fault detector for power amplifiers of a communication system. The fault detector can detect a portion of the power amplifiers that are in fault condition and can prevent or limit current flow to the power amplifiers in fault condition while allowing the rest of the power amplifiers to operate normally. The fault detector can further indicate which power amplifiers are in fault condition and/or the cause for the power amplifiers to be in fault condition. Based on the indication, a controller can direct communications away from the power amplifiers in fault condition and/or perform operations to correct the fault condition.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: August 22, 2023
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventor: Bernhard Strzalkowski
  • Patent number: 11736071
    Abstract: Certain aspects of the present disclosure provide an amplifier. The amplifier generally includes an amplifier core circuit configured to amplify a radio frequency signal and having a first output and a second output; a transformer coupled to the amplifier core circuit, the transformer having a primary winding and a secondary winding, the primary winding being coupled to the first output and the second output of the amplifier core circuit, the secondary winding being coupled to an output node of the amplifier; and a variable resistance circuit coupled in parallel with the primary winding.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: August 22, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Ayush Mittal, Sreenivasa Mallia, Arpit Gupta, Krishnaswamy Thiagarajan, Bhushan Shanti Asuri
  • Patent number: 11736080
    Abstract: A voltage-to-current converter circuit comprises an amplifier, a resistor, first and second feedback circuits, and an output circuit. The amplifier is configured to receive a differential input voltage signal. The resistor is coupled between first and second nodes of the amplifier. The first feedback circuit is coupled to a third node of the amplifier, provides feedback to the first and second nodes when the value of the input voltage signal is in a first range, and is turned off otherwise. The second feedback circuit is coupled to a fourth node of the amplifier, provides feedback to the first and second nodes when the value of the input voltage signal is in a second range different from the first range, and is turned off otherwise. The output circuit produces a differential current output signal having a value according to the value of the input voltage signal.
    Type: Grant
    Filed: December 8, 2022
    Date of Patent: August 22, 2023
    Assignee: NEWRACOM, INC
    Inventor: Seong-Sik Myoung
  • Patent number: 11736076
    Abstract: An average power tracking (APT) power management circuit is provided. The APT power management circuit is configured to generate a first APT voltage(s) for a first power amplifier(s) and a second APT voltage(s) for a second power amplifier(s). The APT power management circuit further includes a pair of switcher circuits that can generate a pair of reference voltages. Depending on various operating scenarios of the APT power management circuit, it is possible to selectively output any of the reference voltages as any one or more of the first APT voltage(s) and the second APT voltage(s). As such, it is possible to flexibly configure the APT power management circuit to support the various operating scenarios based on a minimum possible number of the switcher circuits, thus helping to reduce footprint and cost of the APT power management circuit.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: August 22, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Michael R. Kay
  • Patent number: 11736074
    Abstract: A circuit including an amplifier having an input and an output; and a feedback path comprising a transmission line electrically coupled or electrically connected to the output and the input. A low noise amplifier including the circuit wherein the feedback path cancels noise generated in the low noise amplifier.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 22, 2023
    Assignee: The Regents of the University of California
    Inventors: Tianchi Zeng, Kenneth Pedrotti
  • Patent number: 11716056
    Abstract: A system includes a first differential amplifier and a first transformer with a primary coil coupled to an output of the first differential amplifier and with a secondary coil coupled to a load. The system also includes a second differential amplifier and a second transformer with a primary coil coupled to an output of the second differential amplifier and with a secondary coil coupled in series with the secondary coil of the first transformer. The system also includes a tuning network coupled to a center tap node between the secondary coil of the first transformer and the secondary coil of the second transformer.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: August 1, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tolga Dinc, Sachin Kalia, Swaminathan Sankaran, Baher Haroun
  • Patent number: 11699978
    Abstract: Doherty radio frequency (RF) amplifier circuitry includes an input node, an output node, a main amplifier path, and a peaking amplifier path. The main amplifier path is coupled between the input node and the output node and includes a main amplifier. The peaking amplifier path is coupled in parallel with the main amplifier path between the input node and the output node, and includes a peaking amplifier and a peaking variable gain preamplifier between the input node and the peaking amplifier. The peaking variable gain preamplifier is configured to adjust a current provided to the peaking amplifier.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: July 11, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Dirk Robert Walter Leipold
  • Patent number: 11695376
    Abstract: A phase-synchronized RF power generator includes: an RF power amplifier for amplifying an RF power signal; a first directional coupler; an isolator for adjusting impedance mismatch generated by the first directional coupler, and transferring the RF power signal transferred by the first directional coupler to the output terminal; a second directional coupler for transferring part of the feedback signal transferred by the first directional coupler to be compared with a frequency of a reference signal provided by a crystal oscillator, and transferring rest of the feedback signal to a feedback loop; a digital phase shifter for adjusting a phase of the feedback signal transferred by the second directional coupler at predetermined intervals; an analog phase shifter for continuously adjusting the phase of the feedback signal discretely adjusted by the digital phase shifter; and a frequency comparator.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: July 4, 2023
    Assignee: WAVEPIA CO., LTD.
    Inventor: Sang-Hun Lee
  • Patent number: 11695375
    Abstract: An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a III-V semiconductor substrate, a first RF signal input terminal, a first RF signal output terminal, and a transistor (e.g., a GaN FET). The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: July 4, 2023
    Assignee: NXP USA, Inc.
    Inventors: Joseph Gerard Schultz, Yu-Ting David Wu, Nick Yang
  • Patent number: 11689163
    Abstract: A load-insensitive power amplifier power detector that excludes the use of couplers is disclosed. The load-insensitive power amplifier power detector may include a voltage sampling circuit in electrical communication with a collector of a power amplifier and configured to sample a first voltage from the power amplifier. The load-insensitive power amplifier power detector may include a current sampling circuit in electrical communication with the collector of the power amplifier and configured to sample an output current from the power amplifier. Further, the load-insensitive power amplifier power detector may include a current-to-voltage converter connected between the voltage sampling circuit and an output of the load-insensitive power amplifier power detector. The current-to-voltage converter may be configured to convert the output current to obtain a second voltage.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 27, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventor: Apostolos Samelis
  • Patent number: 11689166
    Abstract: A combination amplifier can include a “main amplifier circuit” for signal amplification, and a matching “compensation amplifier circuit” to monitor distortion in the main amplifier output signal. The compensation amplifier circuit provides a compensation signal to the main amplifier circuit to compensate for and servo out distortion therein. The compensation amplifier circuit includes a passive input network and an amplifier. The passive input network can connect to both the input and output nodes of the main amplifier circuit such that the input and output signals cancel within the passive input network, leaving only the low level distortion component introduced in the main amplifier. Thus, the compensation amplifier is then only operating on the low-level distortion introduced in the main amplifier to generate the compensation signal. Because the compensation amplifier is then only operating on the very low distortion signal, any distortion it introduces into the compensation signal is negligible.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: June 27, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventor: Christopher Peter Hurrell
  • Patent number: 11689160
    Abstract: Techniques are disclosed to compensate for changes in the impedance of stage(s) preceding a trans-impedance amplifier (TIA) that is used within an RF chain. The techniques identify the changes in the source impedance value of the input stage (e.g., the mixers and LNAs) as a result of a gain state change, which alters the signal-to-transfer function (STF) of the TIA during operation and negatively impacts radio performance. The STF is maintained for changes in the source impedance value throughout different gain states without using switchable shunt components by using tunable elements to compensate for the source impedance changes, thus keeping the STF constant.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventor: Daniel Wimmer
  • Patent number: 11683013
    Abstract: Apparatus and methods for power amplifier bias modulation for low bandwidth envelope tracking are provided herein. In certain embodiments, a power amplifier system for a mobile device includes a power amplifier that amplifies an RF signal and a low bandwidth envelope tracker that generates a power amplifier supply voltage for the power amplifier based on an envelope of the RF signal. The envelope tracking system further includes a bias modulation circuit that modulates a bias signal of the power amplifier based on a voltage level of the power amplifier supply voltage.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: June 20, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Serge Francois Drogi, Philip John Lehtola, Florinel G. Balteanu
  • Patent number: 11677363
    Abstract: A power amplifier circuit includes a first transistor configured to receive a first signal at a base, amplify the first signal, and output a second signal from a collector; and a bias circuit configured to supply a bias current to the base of the first transistor. The bias circuit includes a second transistor configured to supply a bias current to the base of the first transistor, a third transistor including a base connected to a base of the second transistor and a collector connected to a collector of the second transistor, and a fourth transistor including a base connected to an emitter of the third transistor and a collector connected to an emitter of the second transistor and configured to draw at least part of the bias current.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: June 13, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuri Honda, Fumio Harima, Mitsuhiro Toya
  • Patent number: 11677367
    Abstract: A power amplifier circuit includes a power splitter, a first amplifier configured to output a first amplified signal from a first output terminal, and a second amplifier configured to output a second amplified signal from a second output terminal. The power amplifier circuit further includes a first termination circuit connected between the first output terminal and the second output terminal, a first transmission line, a second transmission line, a second termination circuit connected between another end of the first transmission line and another end of the second transmission line, and a power combiner.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: June 13, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuri Honda, Satoshi Goto, Fumio Harima
  • Patent number: 11677357
    Abstract: Envelope tracking systems with modeling for power amplifier supply voltage filtering are provided herein. In certain embodiments, an envelope tracking system includes a supply voltage filter, a power amplifier that receives a power amplifier supply voltage through the supply voltage filter, and an envelope tracker that generates the power amplifier supply voltage. The power amplifier provides amplification to a radio frequency (RF) signal that is generated based on digital signal data, and the envelope tracker generates the power amplifier supply voltage based on an envelope signal corresponding to an envelope of the RF signal. The envelope tracking system further includes digital modeling circuitry that models the supply voltage filter and operates to digitally compensate the digital signal data for effects of the supply voltage filter, such as distortion.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: June 13, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventors: Serge Francois Drogi, Florinel G. Balteanu, Shayan Farahvash