Abstract: In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed into a pattern of a polygon spiral. An embodiment of the pattern of the resistor includes sides and corners. The material of the sides has a low resistivity and the material of the corners has a higher resistivity.

Abstract: Three-dimensional capacitive structures may be produced by forming a capacitive stack conformally over pores in a region of porous anodic oxide. The porous anodic oxide region is provided on a stack of electrically-conductive layers including an anodization-resistant layer and an interconnection layer. In the pores there is a position having restricted diameter quite close to the pore bottom. In a first percentage of the pores in the region of anodic oxide, a functional portion of the capacitive stack is formed so as to extend into the pores no further than the restricted-diameter position. Cracks that may be present in the anodization-resistant layer have reduced effect on the properties of the capacitive structure. Increased thickness of the anodization-resistant layer can be tolerated, enabling equivalent series resistance of the overall capacitive structure to be reduced.

Abstract: The present disclosure provides a display device and a display method thereof. The display device includes a microlens array including a plurality of microlenses; and a display panel including a plurality of pixel islands, wherein the plurality of pixel islands are arranged in one-to-one correspondence with the plurality of microlenses, each pixel island includes a plurality of sub-pixels, light emitted by the plurality of sub-pixels of each pixel island enters a human eye through a microlens corresponding to the each pixel island and forms an image in the human eye, and regions where images formed by at least two pixel islands in the plurality of pixel islands via microlenses corresponding to the at least two pixel islands are located are connected.

Abstract: A display apparatus includes a display area including pixels on a substrate, a pad portion on the substrate in a non-display area outside the display area, and including a conductive line, a first dummy line around the conductive line, and a first anti-fuse and a second anti-fuse adjacent to the conductive line and spaced apart from each other in a lengthwise direction of the conductive line, the first anti-fuse and the second anti-fuse each including a first electrode electrically connected to a portion of the conductive line, and a second electrode over the first electrode with a first insulating layer therebetween, and electrically connected to a portion of the first dummy line, and a circuit portion overlapping, and electrically connected to, the pad portion.

Abstract: The present disclosure provides a flexible microwave power transistor and a preparation method thereof. In view of great lattice mismatch and poor performance of a device prepared with a Si substrate in an existing preparation method, the preparation method of the present disclosure grows a gallium nitride high electron mobility transistor (GaN HEMT) layer on a rigid silicon carbide (SiC) substrate to avoid lattice mismatch between a silicon (Si) substrate and gallium nitride (GaN), improving performance of the flexible microwave power transistor. Moreover, in view of problems such as low output power, power added efficiency and power gain with the existing device preparation method, the present disclosure retains part of the rigid SiC substrate and grows a flexible substrates at room temperature to prepare a high-quality device. The present disclosure has greatly improved power output capability, efficiency and gain, and basically unchanged performance of device under 0.75% of stress.

Abstract: The present application provides a method for detecting a broken fanout wire of a display substrate, and a display substrate, and belongs to the field of display technology. In the method for detecting a broken fanout wire, the display substrate includes a base substrate having first and second surfaces opposite to each other, and a plurality of connection structures disposed at intervals on the first surface; and each connection structure includes first and second pads and a fanout wire electrically connecting the first pad to the second pad. The method for detecting a broken fanout wire includes: forming at least one detection unit, which includes: connecting at least two connection structures in series through a connecting part; and measuring a head and an end of the detection unit to obtain resistance of the detection unit, and determining whether there is a broken fanout wire in the detection unit.

Abstract: A method includes etching a through-substrate via (TSV) in a substrate from a backside of the substrate. The substrate has a device layer on a frontside. The method further includes depositing a conformal spacer layer on the backside of the substrate, and sidewalls and a bottom of the TSV, and etching the spacer layer to form a self-aligned mask for etching a contact opening at the bottom of TSV to a metal pad in the device layer, and etching the contact opening at the bottom of TSV to the metal pad in the device layer. The method further includes disposing a conductive material layer in the TSV and the contact opening to make a vertical interconnection from the backside of the substrate to the metal pad in the device layer.

Abstract: A display device including a base layer, a circuit layer, a light emitting device layer, an organic layer, and a touch sensing unit. The base layer includes a display area and a non-display area. A plurality of insulation patterns overlaps the non-display area. The organic layer is disposed on the light emitting device and overlaps the plurality of insulation patterns and the organic light emitting diode. At least a portion of the plurality of touch signal lines overlaps the plurality of insulation patterns.

Abstract: A display device includes a through portion passing through a display layer. The display includes a plurality of scan lines above the substrate and extending in a first direction, a plurality of data lines extending in a second direction, and a plurality of pixels connected to the scan lines and data lines. The data lines include a first data line and a second data line disconnected by the through portion, and a third data line spaced apart from the through portion along the first direction. The first data line is electrically connected with the third data line.

Abstract: A semiconductor device includes a gate-all-around field effect transistor (GAA FET). The GAA FET includes channel regions made of a first semiconductor material disposed over a bottom fin layer made of a second semiconductor material, and a source/drain region made of a third semiconductor material. The first semiconductor material is Si1-xGex, where 0.9?x?1.0, and the second semiconductor material is Si1-yGey, where y<x and 0.3?y?0.7.

Abstract: A header for a semiconductor package includes: an eyelet having an upper surface and a lower surface; a first metal block molded integrally with the eyelet, protruding at the upper surface, and having a substantially U shape; a first lead sealed in a first through hole penetrating the eyelet; a first substrate having a front surface formed with a first signal pattern electrically connected to the first lead and having a back surface fixed to a first end surface of the first metal block; a second lead sealed in a second through hole penetrating the eyelet; and a second substrate having a front surface formed with a second signal pattern electrically connected to the second lead and having a back surface fixed to a second end surface of the first metal block.

Abstract: An organic light emitting diode display panel in this disclosure comprises a base substrate, an array layer disposed on the base substrate, and a planarization layer disposed on the array layer. The OLED display panel further comprises anodes disposed on the planarization layer, and a pixel definition layer located between the anodes adjacent to each other. A luminescent layer, a cathode, and an encapsulation layer are provided on the anodes. A preparation material of the pixel definition layer is a light-shading material. By the pixel definition layer made of a light-shading material, the light shading effect of the OLED display panel is greatly enhanced, and the influence of the lateral light leakage of the OLED display panel on the TFT device is prevented.

Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.

Abstract: An organic light-emitting diode (“OLED”) includes a bottom electrode, a top electrode disposed opposite to the bottom electrode, and an organic layer that is interposed between the bottom electrode and the top electrode and includes a hole-transporting host and an electron-transporting host forming an exciplex and a phosphorescent dopant having a triplet energy which is lower than the triplet energy of the hole-transporting host, the triplet energy of the electron-transporting host, and the triplet energy of the exciplex, and a lighting device and a display apparatus including the OLED. Instead of a phosphorescent dopant, the fluorescent dopant having a singlet energy which is lower than the singlet energy of the exciplex may be also used.

Abstract: A light emitting device includes: a base; a first terminal and a second terminal located at a surface of the base; a light emitting element array chip mounted on the base, the light emitting element array chip including: a support substrate, a plurality of first wirings and a plurality of second wirings disposed on the support substrate, and a plurality of light emitting elements, each of the light emitting elements arranged on the first wiring and the second wiring and electrically connected to the first wiring and the second wiring; and a plurality of wires including a first wire connecting the first wiring to the first terminal, and a second wire connecting the second wiring to the second terminal.

Abstract: In the embodiments of the present invention, a glass substrate in a micro display panel includes a first surface and a second surface arranged opposite to one another, and a first terminal and a second terminal arranged opposite to one another. An insulation layer disposed on the first surface. A thin film transistor layer disposed on a surface of the insulation layer away from the glass substrate. A micro light-emitting diode layer disposed on a surface of the thin film transistor layer away from the insulation layer. A terminal of the insulation layer, the thin film transistor layer, and the micro light-emitting diode layer close to the first terminal is bent toward a side away from the second surface, and an interval is defined between a terminal of the insulation layer close to the first terminal and the first terminal.

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, and a side surface between the first and second surfaces, and including a device region on the first surface a wiring structure on the surface of the semiconductor substrate, and having a dielectric layer and a metal wiring in the dielectric layer and electrically connected to the device region, and an insulating material layer on a side surface of the wiring structure and having a side surface connected to the side surface of the semiconductor substrate. The side surface of the insulating material layer has a first wave-shaped pattern in which concave-convex portions are repeated in a direction of the wiring structure that is perpendicular to the semiconductor substrate, and the side surface of the semiconductor substrate has a second wave-shaped pattern in which concave-convex portions are repeated in the direction.

Abstract: The present disclosure is directed to methods for producing a photovoltaic junction that can include coating a bare junction with a composition. In one embodiment, the composition includes a plurality of quantum dots to create a film; exposing the film to a ligand to create a first layer; coating the first layer with the composition to form a film on the first layer; and exposing the film on the first layer to the ligand to create a second layer.

Abstract: Semiconductor devices are provided. A semiconductor device includes gate electrodes on a substrate and stacked perpendicularly to an upper surface of the substrate. The semiconductor device includes interlayer insulating layers alternately stacked with the gate electrodes. Moreover, the semiconductor device includes channel structures passing through the gate electrodes. Each of the channel structures includes a channel layer extending perpendicularly to the upper surface of the substrate, a tunneling insulating layer on the channel layer, charge storage layers on the tunneling insulating layer in respective regions between the gate electrodes and a side surface of the tunneling insulating layer, and first blocking insulating layers on the charge storage layers, respectively. A first layer of the first blocking insulating layers is on an upper surface, a lower surface, and a side surface of a first layer of the charge storage layers.

Abstract: A display panel and a manufacturing method of a display panel are provided. The display panel includes a display area and a non-display area disposed on one side of the display area. A driving chip and a fanout wiring area are disposed in the non-display area. A fanout line module is disposed in the fanout wiring area. The fanout line module includes a first wiring area and a second wiring area. A first signal line connecting the data line is disposed in the first wiring area. A second signal line connecting the gate line and another first signal line connecting the data line are disposed in the second wiring area.