Abstract: The present disclosure is directed to methods for producing a photovoltaic junction that can include coating a bare junction with a composition. In one embodiment, the composition includes a plurality of quantum dots to create a film; exposing the film to a ligand to create a first layer; coating the first layer with the composition to form a film on the first layer; and exposing the film on the first layer to the ligand to create a second layer.

Abstract: A display panel and a manufacturing method of a display panel are provided. The display panel includes a display area and a non-display area disposed on one side of the display area. A driving chip and a fanout wiring area are disposed in the non-display area. A fanout line module is disposed in the fanout wiring area. The fanout line module includes a first wiring area and a second wiring area. A first signal line connecting the data line is disposed in the first wiring area. A second signal line connecting the gate line and another first signal line connecting the data line are disposed in the second wiring area.

Abstract: Semiconductor devices are provided. A semiconductor device includes gate electrodes on a substrate and stacked perpendicularly to an upper surface of the substrate. The semiconductor device includes interlayer insulating layers alternately stacked with the gate electrodes. Moreover, the semiconductor device includes channel structures passing through the gate electrodes. Each of the channel structures includes a channel layer extending perpendicularly to the upper surface of the substrate, a tunneling insulating layer on the channel layer, charge storage layers on the tunneling insulating layer in respective regions between the gate electrodes and a side surface of the tunneling insulating layer, and first blocking insulating layers on the charge storage layers, respectively. A first layer of the first blocking insulating layers is on an upper surface, a lower surface, and a side surface of a first layer of the charge storage layers.

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, and a side surface between the first and second surfaces, and including a device region on the first surface a wiring structure on the surface of the semiconductor substrate, and having a dielectric layer and a metal wiring in the dielectric layer and electrically connected to the device region, and an insulating material layer on a side surface of the wiring structure and having a side surface connected to the side surface of the semiconductor substrate. The side surface of the insulating material layer has a first wave-shaped pattern in which concave-convex portions are repeated in a direction of the wiring structure that is perpendicular to the semiconductor substrate, and the side surface of the semiconductor substrate has a second wave-shaped pattern in which concave-convex portions are repeated in the direction.

Abstract: The present inventive concept relates to a display device. A display device according to an exemplary embodiment of the present inventive concept include: a base layer including a plurality of islands in which a pixel is disposed, a plurality of bridges disposed around each of the plurality of islands, a plurality of first wires disposed in a bridge of the plurality of bridges connected to the pixel is disposed; an inorganic insulating layer disposed on the base layer and having an opening exposing a portion of the bridge; and an organic material layer covering the opening, wherein adjacent islands of the plurality of islands are connected to each other through at least the bridge of the plurality of bridges, and the plurality of first wires are disposed on the organic material layer.

Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

Abstract: In general aspect, a semiconductor device package can include a substrate and a semiconductor die disposed on and coupled with the substrate. The semiconductor device package can further include a leadframe having an indentation defined therein, at least a portion of the indentation being disposed on and coupled with the semiconductor die via a conductive adhesive.

Abstract: Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.

Abstract: Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The multiple transistors may include multiple P-type transistors that are arranged in a P-over-P stack configuration, and the multiple transistors may include multiple N-type transistors that are arranged in an N-over-N stack configuration.

Abstract: A semiconductor package includes a semiconductor die, an encapsulant, a first and second dielectric layer, a through via, an extension pad, and a routing via. The semiconductor die includes a contact post. The first dielectric layer extends on the encapsulant. The through via extends through the first dielectric layer and has one end contacting the contact post. The extension pad is disposed on the first dielectric layer, contacting an opposite end of the through via with respect to the contact post. The extension pad has an elongated shape, a first end of the extension pad overlaps with the contact post and the through via, and a second end of the extension pad overlaps with the encapsulant. The second dielectric layer is disposed on the first dielectric layer and the extension pad. The routing via extends through the second dielectric layer to contact the second end of the extension pad.

Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.

Abstract: The present disclosure belongs to the technical field of integrated circuit packaging, and specifically relates to a through silicon via structure for three-dimensional integrated circuit packaging and a manufacturing method thereof.

Abstract: Disclosed is a low temperature method of fabrication of short-wave infrared (SWIR) detector arrays (FPA) including a readout wafer and absorption layer connected for improved performances. The absorber layer includes a SWIR conversion layer with a GeSn or SiGeSn alloy. A first series of process steps realizes a CMOS processed readout wafer. A buffer layer is transferred on the readout wafer and annealed at temperatures compatible with the CMOS substrate, achieving a high quality crystalline buffer layer. The method assures a temperature profile between the light entrance surface of the buffer layer, and the readout electronics so the annealing temperature remains compatible with the CMOS. The buffer layer is used for further growth of a GeSn or SiGeSn structure to create the conversion layer and achieve the final structure of the SWIR FPA. Also disclosed is a SWIR FPA detector as realized by such method, and SWIR FPA applications.

Abstract: One aspect of the invention relates to a multi-terminal memtransistor. The memtransistor includes a substrate having a first surface and an opposite, second surface, a polycrystalline monolayer film formed of an atomically thin material on the first surface of the substrate, an electrode array having a plurality of electrodes spatial-apart formed on the polycrystalline monolayer film such that each pair of electrodes defines a channel in the polycrystalline monolayer film therebetween, and a gate electrode formed on the second surface of the substrate and capacitively coupled with the channel. The polycrystalline monolayer film contains grains defining a plurality of grain boundaries thereof. The multi-terminal memtransistor operates much like a neuron by performing both memory and information processing, and can be a foundational circuit element for new forms of neuromorphic computing.

Abstract: Provided is a semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device being configured to route signals, a second semiconductor device provided on a second surface of the wafer opposite to the first surface of the wafer, the second semiconductor device being configured to supply power, and a buried power rail (BPR) included inside of the wafer and extending from the first surface of the wafer to the second surface of the wafer, the BPR being configured to deliver the power from the second semiconductor device to the first semiconductor device.

Abstract: Microelectronic devices, assemblies, and systems include a microelectronic die and composite material to conduct heat from the microelectronic die such that the composite material includes polymer chains chemically bonded to fill particles having a hexagonal lattice of carbon atoms such as graphene sheet fill particles and/or carbon nanotube fill particles.

Abstract: Provided herein is: a SiC substrate having a front surface on which a GaN layer is stacked; a source electrode formed on a front surface of the GaN layer; a MIM capacitor formed on a front surface of the source electrode; and a via hole extending from a rear surface of the SiC substrate to reach the source electrode; wherein a barrier metal layer is included in the source electrode, and wherein the depth end of the via hole is placed between a rear surface of the source electrode and a rear surface of the barrier metal layer. Accordingly, intrusion of a halogen element, in particular, Br, into an insulating film that is placed in the MIM capacitor, is suppressed over a long term.

Abstract: A method of manufacturing a display apparatus includes preparing a panel with a panel layer displaying images, a first protection film on a first surface of the panel layer with a first adhesion layer, and a second protection film on a second surface of the panel layer with a second adhesion layer, disposing the panel on a stage, cutting the panel on the stage along a closed-curve line to a predetermined depth extending from the second protection film to at least a portion of the first adhesion layer, and separating a first portion of the panel inside the closed-curve line from a second portion of the panel outside the closed-curve line, such that the second portion is removed simultaneously with the entire first protection film according to a first boundary by the line and a second boundary between the panel layer and the first protection film.

Abstract: An apparatus is provided which comprises: a first transistor comprising a source region and a drain region with a channel region therebetween, a first dielectric layer over the first transistor, a second transistor comprising a source region and a drain region with a channel region therebetween, wherein the second transistor is over the first dielectric layer, a second dielectric layer over the second transistor, and a contact coupled to the source region or the drain region of the first transistor, wherein the contact comprises a metal having a straight sidewall that extends from through both the first and second dielectric layers. Other embodiments are also disclosed and claimed.

Abstract: An electronic device is disclosed. The electronic device includes a substrate, a first electrode and a second electrode disposed on the substrate, a plurality of electronic units comprising a first electronic unit corresponding to a sub-pixel, a second electronic unit corresponding to another sub-pixel, wherein the first electrode and the second electrode are electrically connected to the first electronic unit and the second electronic unit, and the second electrode is electrically insulated from the first electrode.