Abstract: A device information writing circuit features a redundancy fuse set for selectively performing a repair operation or a device information writing operation. The repair operation is performed with a fuse set having the least frequency of use from the redundancy fuse sets of a row address. Additionally, the number of fuse sets is reduced because the device information including the LOT number, the wafer number and row/column coordinates is written as different data in each bank by a fuse cutting method.

Abstract: A nonvolatile memory device features a serial diode cell by effectively arranging a cross point cell array including a nonvolatile ferroelectric capacitor and a serial PN diode chain to reduce the whole memory size. A serial diode cell array including a nonvolatile ferroelectric capacitor and a serial diode switch which does not require an additional gate control signal is positioned on a circuit device region including a word line driving unit, a sense amplifier, a data bus, a main amplifier, a data buffer and an input/output port. An interlayer insulating film separates a cell array region and the circuit device region, thereby reducing the whole chip size.

Abstract: The present invention discloses a non-volatile ferroelectric cell array circuit using PNPN diode characteristics. The non-volatile ferroelectric cell array circuit includes a plurality of top sub cell arrays, a plurality of bottom sub cell arrays, a main bit line sense amp and a word line driving unit. Especially, the top and bottom sub cell arrays have a double bit line sensing structure for inducing a sensing voltage of a main bit line by controlling an amount of a current supplied from a power voltage to the main bit line according to a sensing voltage of a sub bit line receiving a cell data. Each of the sub cell arrays includes a ferroelectric capacitor, and a serial PN diode switch having a PNPN diode and a PN diode, to decrease a cell size and improve operational characteristics of the circuit.

Abstract: A NOR-type flash memory device includes a global decoder circuit that is coupled to global wordlines. The global decoder circuit drives the global wordlines using wordline voltages that will be applied to local wordlines in each operation mode, and has wordline select switches each corresponding to the global wordlines. A local decoder circuit couples the local wordlines to the global wordlines in response to a sector select signal, and a sector generates a control signal in accordance with address information for selecting a memory cell array. A switch circuit includes a plurality of depletion MOS transistors each being coupled between corresponding first and second wordline. The depletion MOS transistors are commonly controlled by a control signal. Each of the wordline select switches is made of two NMOS transistors.

Abstract: A synchronous memory device and a synchronous multi-port memory device preventing a skew between data and data strobe signal according to data transmission path is disclosed. In order to eliminate such a position dependence, the synchronous memory device and the synchronous multi-port memory device adopt a scheme of transmitting the data strobe signal together with the data. If a data driving block transmits the data capture pulse together with the data, the data and the data capture pulse pass the same delay without regard to the data transmission/reception blocks, thus preventing the occurrence of the skew. In other words, the present invention adopts a source synchronization scheme, which is used at an outside of the conventional synchronous DRAM, into the memory device. Specifically, the present invention can be applied to a synchronous multi-port memory device having a plurality of independent ports.

Abstract: A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through a first resistor. The first memory node is coupled to an input of the second inverter through a second resistor. A pair of access transistors are respectively coupled to a pair of bit lines, a split word line and one of the memory nodes. The resistors are prepared by coating a layer of silicide material on a selective portion of the gate structure of the transistors included in the first inverter, and connecting a portion of the gate structure that is substantially void of the silicide material to the drain of the transistors included in the second inverter.

Abstract: Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ?, or 1/16) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

Abstract: Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.

Abstract: A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising voltage rate of a reference multiple matchline in order to generate a multibit result representing one of the three conditions. The circuit generates a self-timed control signal to end the search-and-compare operation, and to set the circuit to a precharge state.

Abstract: A memory cell array is partitioned into a plurality of memory regions each of which includes a plurality of sense amplifiers and each of which is established as a unit of data input/output. Dummy regions each are formed between every two memory regions and include dummy bit lines that are set to a predetermined voltage at least during the operation of the memory cell array. Since the dummy bit lines are wired between the bit lines of the two adjacent memory regions, the voltage change in the bit lines in any of the memory regions can be prevented from affecting the bit lines in the other memory regions. As a result, malfunction of semiconductor memories can be prevented.

Abstract: A synchronous memory device which generates a data output enable signal corresponding to a set CAS latency mode including: a control clock generator for generating an A-type first control clock and a B-type first control clock; a first redundancy enable signal generator for shifting an internal read signal by a predetermined interval in synchronization with one of the A-type first control clock and the B-type first control clock and generating a plurality of first redundancy enable signals; a second redundancy enable signal generator for synchronizing the plurality of first redundancy enable signals with a DLL clock and generating a plurality of second redundancy enable signals; and an output enable signal generator for selecting one redundancy enable signal corresponding to the set CAS latency mode among the first redundancy enable signals and the second redundancy enable signals and generating the selected redundancy enable signal as the data output enable signal.

Abstract: A method of programming a nonvolatile memory cell in which a ramped control voltage is used to obtain the desired voltage on the storage node.

Abstract: A semiconductor memory device includes a first magneto resistive element disposed in a memory cell portion, a first circuit disposed in the memory cell portion, the first circuit writing data into the first magneto resistive element or reading out data from the first magneto resistive element, and at least a portion of a second circuit disposed in a region below the memory cell portion.

Abstract: In each of output buffer circuits arranged corresponding to respective output pads, a first output buffer having small current driving capability for a normal operation mode and a second output buffer having large current driving capability for a test operation mode are arranged in parallel with each other. One of the first and second output buffers is enabled and the other is set to an output high impedance state alternatively in accordance with a mode designating signal. Thus, an output buffer circuit capable of driving an output pad with optimal driving capabilities in a normal operation mode and in a test operation mode in a semiconductor device for use in a system in package is implemented.

Abstract: A digit line architecture for an array of memory cells exhibiting characteristics of both folded digit line architectures and an open digit line architectures. The digit line architecture includes first and second digit lines having first and second digit line segments. The memory cells of a column are coupled to the first digit line segments. The second digit line segment of the first digit line is located in the memory sub-array with which the column is associated and the second digit line segment of the second digit line extending into the other memory sub-array with which the column is not associated.

Abstract: A number of memory array units are placed on a die. Each memory array within a unit is coupled to a channel that includes one or more data lines coupled to a pad on the die. Each memory array unit utilizes a different channel. Memory array units are grouped together in pairs on the die to form memory array groups. The two channels of each memory array group form boundaries on the die. The pads coupled to each channel of a memory array group are positioned within those boundaries. The pads may be arranged such that the same pad layout can be used across different dies fabricated for use at different bus widths. In one embodiment, a set of the pads are used in applications where the die is configured for a first bus width and a portion of the pads used in the first bus width applications are not used in applications where the die is configured to for a second bus width.

Abstract: An FCRAM includes first to third circuits. The first circuit generates a first signal based on a command detection signal. The second circuit is configured to receive the command detection signal, an operation mode specifying signal and a selection signal and generate a second signal which causes the start timing of the operation of a row-system circuit to be synchronized with the input timing of a second command. The third circuit is configured to select the first signal when a normal operation mode is specified by the operation mode specifying signal, select the second signal when a test mode is specified, and generate a third signal used to activate at least part of the memory cells in a memory cell array based on a selected one of the first and second signals and the selection signal.

Abstract: A memory including a memory element having islands is provided. The memory has address decoding circuitry and an array of memory plugs. The memory plugs include memory element that have island structures of a first material within the bulk of a second material. The island structures are typically nanoparticles. The memory plugs can be placed in a first resistive state at a first write voltage, placed in a second resistive state at a second write voltage, and have its resistive state determined at a read voltage.

Abstract: A resistor is connected to a source line of memory cells, a write-back operation is performed to memory cells on a single unit basis. With the resistor connected, there is suppressed, in a self-adjusting manner, channel leakage current flowing in a memory cell having a low threshold voltage in an over-erased state. There is assured an output voltage of a charge pump circuit supplying a drain voltage at a high potential necessary for forming a high electric field for generating sub-threshold CHE (Channel Hot Electron) in memory cells to be singly written back. As a result, a non-volatile semiconductor memory device can suppress a write back fault due to an increase in channel leakage current, in a self-selective write-back method using sub-threshold CHE.

Abstract: A method and apparatus are disclosed for detecting if a semiconductor circuit has been exposed to ultra-violet light. An ultra-violet light detection circuit detects exposure to ultra-violet light and will automatically activate a security violation signal. The security violation signal may optionally initiate a routine to clear sensitive data from memory or prevent the semiconductor circuit from further operation. The ultra-violet light detection circuit detects whether a semiconductor circuit has been exposed to ultra-violet light, for example, by employing a dedicated mini-array of non-volatile memory cells. At least two active bit lines, blprg and bler, are employed corresponding to program and erase, respectively. One of the bit lines is only programmable and the other bit line is only eraseable. Generally, all of the bits in the dedicated non-volatile memory array are initially in approximately the same state, which could be erased, programmed or somewhere in between.