Patents Examined by Hrayr A. Sayadian
  • Integrated circuit packaging system with shielding and method of manufacture thereof
    Patent number: 11024585
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 1, 2021
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, KyoungHee Park, Yaojian Lin, KyoWang Koo, In Sang Yoon, SeungYong Chai, SungWon Cho, SungSoo Kim, Hun Teak Lee, DeokKyung Yang
  • Radio frequency shielding within a semiconductor package
    Patent number: 11018713
    Abstract: Radio frequency shielding within a semiconductor package is described. In one example, a multiple chip package has a digital chip, a radio frequency chip, and an isolation layer between the digital chip and the radio frequency chip. A cover encloses the digital chip and the radio frequency chip.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 25, 2021
    Assignee: Intel IP Corporation
    Inventors: Edmund Goetz, Bernd Memmler, Jan-Erik Mueller, Peter Baumgartner
  • Method of fabricating semiconductor device
    Patent number: 11018132
    Abstract: A method for fabricating a semiconductor device includes the steps of providing a semiconductor substrate; forming a tunnel dielectric on the semiconductor substrate; forming a floating gate on the tunnel dielectric; forming an insulation layer conformally disposed on the top surface and the sidewall surface of the floating gate; forming a control gate disposed on the insulation layer and the floating gate; and forming a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, where the spacer overlaps portions of the top surface of the floating gate.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: May 25, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tzu-Ping Chen, Chien-Hung Chen
  • Transistor with contacted deep well region
    Patent number: 11011615
    Abstract: Various methods and devices that involve body contacted transistors are disclosed. An exemplary method comprises forming a gate on a planar surface of a semiconductor wafer. The gate covers a channel of a first conductivity type that is opposite to a second conductivity type. The method also comprises implanting a body dose of dopants on a source side of the gate using the gate to mask the body dose of dopants. The body dose of dopants spreads underneath the channel to form a deep well. The body dose of dopants has the first conductivity type. The method also comprises implanting, subsequent to implanting the body dose of dopants, a source dose of dopants on the source side of the gate to form a source. The method also comprises forming a source contact that is in contact with the deep well at the planar surface of the semiconductor wafer.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 18, 2021
    Assignee: Silanna Asia Pte Ltd
    Inventor: George Imthurn
  • Ohmic contacts for semiconductor structures
    Patent number: 10998481
    Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, John Mark Meldrim, Shanming Mou, Everett Allen McTeer
  • Gate cut isolation including air gap, integrated circuit including same and related method
    Patent number: 10971583
    Abstract: A gate cut isolation including an air gap and an IC including the same are disclosed. A method of forming the gate cut isolation may include forming an opening in a dummy gate that extends over a plurality of spaced active regions, the opening positioned between and spaced from a pair of active regions. The opening is filled with a fill material, and the dummy gate is removed. A metal gate is formed in a space vacated by the dummy gate on each side of the fill material, and the fill material is removed to form a preliminary gate cut opening. A liner is deposited in the preliminary gate cut opening, creating a gate cut isolation opening, which is then sealed by depositing a sealing layer. The sealing layer closes an upper end of the gate cut isolation opening and forms the gate cut isolation including an air gap.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 6, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Hong Yu, Hui Zang, Jiehui Shu
  • Ball grid array underfilling systems
    Patent number: 10971439
    Abstract: A ball grid array (BGA) assembly can include a component substrate having at least one underfill channel defined therethrough providing fluidic communication between a first side of the component substrate and a second side of the component substrate, a plurality of pads or leads exposed on the second side and configured to be soldered to a mating PCB, a cover mounted to the component substrate defining a reservoir cavity between the first side and the cover, and an underfill material disposed within the reservoir cavity such that the underfill material can flow through the at least one underfill channel to a gap defined between the second side and the mating PCB when the component substrate is being soldered to the mating PCB.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: April 6, 2021
    Assignee: HAMILTON SUNDSTRAND CORPORATION
    Inventor: Eileen A. Bartley
  • Precision capacitor
    Patent number: 10964778
    Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: March 30, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Poornika Fernandes, Luigi Colombo, Haowen Bu
  • Vertical plate capacitors exhibiting high capacitance manufactured with directed self-assembly
    Patent number: 10964779
    Abstract: A semiconductor structure includes a substrate and a first trench including a dielectric material disposed in the substrate. The first trench includes a transferred pattern of a first polymer of a directed self-assembly stack including the first polymer and a second polymer. The semiconductor structure also includes a second trench including a first vertical metal plate disposed in the substrate adjacent a first sidewall of the first trench, and a third trench including a second vertical metal plate disposed in the substrate adjacent a second sidewall of the first trench. The first vertical metal plate in the second trench, the dielectric material in the first trench, and the second vertical metal plate in the third trench provide a metal-insulator-metal vertical plate capacitor.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kafai Lai, Rasit Onur Topaloglu
  • Vertical FET devices with multiple channel lengths
    Patent number: 10957603
    Abstract: A semiconductor device comprises a first source/drain region arranged on a semiconductor substrate, a second source/drain region arranged on the semiconductor substrate, a bottom spacer arranged on the first source/drain region, and a bottom spacer arranged on the second source/drain region. A first gate stack having a first length is arranged on the first source/drain region. A second gate stack having a second length is arranged on the second source/drain region, the first length is shorter than the second length. A top spacer is arranged on the first gate stack, and a top spacer is arranged on the second gate stack.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hari V. Mallela, Reinaldo A. Vega, Rajasekhar Venigalla
  • Semiconductor device and manufacturing method of semiconductor device
    Patent number: 10950700
    Abstract: A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: March 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Fabrication of silicon germanium channel and silicon/silicon germanium dual channel field-effect transistors
    Patent number: 10943835
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate, wherein each fin of the plurality of fins includes silicon germanium. A layer of silicon germanium oxide is deposited on the plurality of fins, and a first thermal annealing process is performed to convert outer regions of the plurality of fins into a plurality of silicon portions. Each silicon portion of the plurality of silicon portions is formed on a silicon germanium core portion. The method further includes forming a plurality of source/drain regions on the substrate, and depositing a layer of germanium oxide on the plurality of source/drain regions. A second thermal annealing process is performed to convert outer regions of the plurality of source/drain regions into a plurality of germanium condensed portions.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: ChoongHyun Lee, Kangguo Cheng, Juntao Li, Shogo Mochizuki
  • Light receiving element, optical communication device, and method for manufacturing a light receiving element
    Patent number: 10937919
    Abstract: A light receiving element (1) according to an embodiment of the disclosure includes a semiconductor layer (20) in which a photodiode having a PIN structure is provided in a mesa portion having a pillar shape. The photodiode includes a first conductive layer (21), an optical absorption layer (23), and a second conductive layer (24) having a light incident surface. In the light receiving element (1), the semiconductor layer (20) includes, in the vicinity of an interface between the first conductive layer (21) and the optical absorption layer (23), a constricted portion (26) that is the most constricted of the first conductive layer (21). The interface has an end exposed on an internal surface of the constricted portion (26).
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: March 2, 2021
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Shingo Kaneko
  • Semiconductor device and method of manufacturing the same
    Patent number: 10930695
    Abstract: An imaging device includes a first semiconductor element including at least one bump pad that has a concave shape. The at least one bump pad includes a first metal layer and a second metal layer on the first metal layer. The imaging device includes a second semiconductor element including at least one electrode. The imaging device includes a microbump electrically connecting the at least one bump pad to the at least one electrode. The microbump includes a diffused portion of the second metal layer, and first semiconductor element or the second semiconductor element includes a pixel unit.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: February 23, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Satoru Wakiyama, Kan Shimizu, Toshihiko Hayashi, Takuya Nakamura, Naoki Jyo
  • Substrate, method for manufacturing the same, and display device
    Patent number: 10923683
    Abstract: The embodiments of the present disclosure propose a substrate, a method for manufacturing the same, and a display device comprising the substrate. The substrate comprises a supporting base; and a light scattering layer disposed such that a projected region of the light scattering layer on the supporting base is located in a light transmission formation region of the supporting base, and the light scattering layer has a light scattering structure configured to scatter incident light.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: February 16, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiangxiang Zou, Wei Qin, Kuanjun Peng, Xiaolong Li
  • Semiconductor device
    Patent number: 10916483
    Abstract: An object of the present invention is to provide a semiconductor device having a structure in which a resin hardly enters between an insert electrode and a nut at a time of resin sealing. The semiconductor device according to the present invention includes an insert electrode having an insert hole into which a bolt is inserted from outside, a nut which has a screw hole to be screwed with the bolt and is disposed on an inside of the insert electrode so that the screw hole is communicated with the insert hole, at least one semiconductor element being electrically connected to the insert electrode, and a resin sealing the inside of the insert electrode, the nut, and the at least one semiconductor element, wherein a burr is provided on an outer periphery of a direct contact surface of the nut being in direct contact with the insert electrode.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: February 9, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takahiko Murakami, Mitsunori Aiko, Takaaki Shirasawa, Natsuki Tsuji
  • Base plate, method for manufacturing the same and display panel
    Patent number: 10916602
    Abstract: The embodiments of the present disclosure provide a base plate, a manufacturing method thereof and a display panel, relating to the field of display technology. Ink droplets in grooves defined by a pixel defining layer can be spread uniformly, thereby effectively improving the product quality and the display effect. The base plate comprises a substrate and a pixel defining layer arranged on the substrate, wherein the pixel defining layer comprises dams and several micron-sized protrusions arranged on the upper surfaces and sides of the dams; and the protrusions have lyophobic property.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: February 9, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Shirong Yu, Qingyong Meng, Chunhui Wu
  • Multi pixel micro lens pixel array and camera system for solving color mix and operating method thereof
    Patent number: 10916576
    Abstract: A camera system includes a single lens and an image sensor including a reference pixel array including a plurality of W (white) pixels in a two-dimensional arrangement and a single microlens formed on the plurality of W pixels to be shared, and at least one color pixel array including two W pixels and two color pixels in a two-dimensional arrangement, and a single microlens disposed on the two W pixels and the two color pixels to be shared. Light shielding layers formed with Offset Pixel Apertures (OPAs) are disposed on the plurality of W pixels included in the reference pixel array and the two W pixels included in the at least one color pixel array, respectively, and the OPAs are formed on the light shielding layers in the reference pixel array and the at least one color pixel array, respectively, to maximize a spaced distance between the OPAs.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: February 9, 2021
    Assignee: CENTER FOR INTEGRATED SMART SENSORS FOUNDATION
    Inventors: Chong Min Kyung, Seung Hyuk Chang, Won Seok Choi
  • Semiconductor integrated device with electrical contacts between stacked dies and corresponding manufacturing process
    Patent number: 10906801
    Abstract: An integrated device includes: a first die; a second die coupled in a stacked way on the first die along a vertical axis; a coupling region arranged between facing surfaces of the first die and of the second die, which face one another along the vertical axis and lie in a horizontal plane orthogonal to the vertical axis, for mechanical coupling of the first and second dies; electrical-contact elements carried by the facing surfaces of the first and second dies, aligned in pairs along the vertical axis; and conductive regions arranged between the pairs of electrical-contact elements carried by the facing surfaces of the first and second dies, for their electrical coupling. Supporting elements are arranged at the facing surface of at least one of the first and second dies and elastically support respective electrical-contact elements.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: February 2, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Enri Duqi, Lorenzo Baldo, Domenico Giusti
  • Display device and method of manufacturing the same
    Patent number: 10910605
    Abstract: In a method of manufacturing a display device, the method includes: forming a conductive layer on a base; forming an organic layer, with a hole partially exposing the conductive layer, on the conductive layer; polishing an upper surface of the organic layer; and forming a light emitting element on the polished organic layer.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: February 2, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joon Hwa Bae, Hyun Jin Cho, Byoung Kwon Choo, Woo Jin Cho