Abstract: A method for manufacturing a semiconductor structure that comprises providing a monocrystalline silicon base layer comprising a first region for manufacturing the III-N semiconductor device and a second region for manufacturing the silicon semiconductor device; providing on the monocrystalline silicon base layer a mask layer, the mask layer being interrupted, in the first region, by a recess in the monocrystalline silicon base layer, wherein the mask layer comprises a 2D material; forming, selectively, a layer of gamma-Al2O3 at the bottom of the recess by a first growth process; forming, selectively on the layer of gamma-Al2O3, a III-N semiconductor device stack by a second growth process, and thereafter; manufacturing, in the second region, at least partially a silicon semiconductor device.

Abstract: This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z1/2 in a portion is not more than 1×1011 cm?3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×1018 cm?3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×1018 cm?3.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer including Alx1Ga1-x1N (0?x1<1), a second semiconductor layer including Alx2In1-x2N (0<x2<1 and x1<x2), and an intermediate region provided between the first and second semiconductor layers. The intermediate region includes Alx3Ga1-x3N (0<x3?1 and x2<x3). The second semiconductor layer includes first and second surfaces. The second surface is between the intermediate region and the first surface in a first direction. The first direction is from the first semiconductor layer toward the second semiconductor layer. The second semiconductor layer includes a plurality of first pits provided in the first surface. Widths of the first pits are 200 nm or more. A density in the first surface of the first pits is not less than 5×107/cm2 and not more than 1×108/cm2.

Abstract: The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-AlyGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-AlyGaN layer to the junction between the i-GaN channel layer and the i-AlxGaN layer.

Abstract: Systems and methods are described herein for the variable and dynamic control of a variable aperture masking unit to define, isolate and/or mask diffusion areas for dopant implantation and/or thermal annealing processes useful in wafer fabrication in the production of advanced semiconductor devices. A plurality of isolation material panels can be dynamically positioned to define a size, position and shape of a variable mask aperture between edges of the plurality of isolation material panels. The isolation material panels are connected between cooperating pairs of carriers that are coupled to and travel along a set of parallel tracks on opposite sides of the variable aperture masking unit.

Abstract: Processing methods may be performed to produce semiconductor structures. The methods may include forming a silicon layer over a semiconductor substrate. The forming may include forming a silicon layer incorporating a dopant. The methods may include oxidizing a portion of the silicon layer while maintaining a portion of the silicon layer in contact with the semiconductor substrate. The oxidizing may drive a portion of the dopant through the silicon layer and into the semiconductor substrate.

Abstract: A semiconductor device of an embodiment includes a first electrode; a second electrode; and a silicon carbide layer disposed between the first electrode and the second electrode, and includes a first silicon carbide region of n-type; and a second silicon carbide region disposed between the first silicon carbide region and the first electrode, in contact with the first electrode, containing an at least one element selected from the group consisting of sulfur (S), selenium (Se), tellurium (Te), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), and tungsten (W), and containing at least one first atom of the at least one element, the first atom being bonded to four silicon atoms.

Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first, second, and third semiconductor layers, and a first insulating member. The first semiconductor layer includes first, second, third, fourth, and fifth partial regions. A direction from the first partial region toward the second partial region is along a first direction. The first electrode includes a first electrode portion. A direction from the first electrode portion toward the second electrode is along the first direction. A second direction from the third partial region toward the third electrode crosses the first direction. The second semiconductor layer includes a first semiconductor portion and a second semiconductor portion. At least a portion of the first semiconductor layer is between the third and second semiconductor layers. The first insulating member includes a first insulating portion. The first insulating portion is provided between the third partial region and the third electrode.

Abstract: A method includes providing a structure having transistors, an isolation structure over the transistors, metal plugs through the isolation structure and connecting to the transistors, and a trench with the isolation structure and the metal plugs as sidewalls. The method further includes forming a dielectric liner on the sidewalls of the trench and over the isolation structure and the metal plugs. The dielectric liner is thicker at an opening portion of the trench than at another portion of the trench so that an air gap is formed inside the trench and the air gap is surrounded by the dielectric liner. The method further includes depositing a sacrificial layer over the dielectric liner and over the air gap and performing CMP to remove the sacrificial layer and to recess the dielectric liner until the isolation structure and the metal plugs are exposed. The air gap remains inside the trench.

Abstract: After trench etching, trench corner portions are rounded by hydrogen annealing at a temperature of at least 1500 degrees C. Next, n-type regions that cause leak current and are formed in inner walls of the trenches by the hydrogen annealing are removed by a heat treatment (hydrogen etching) under a hydrogen atmosphere of a temperature less than 1500 degrees C. and the inner walls are planarized. Next, the inner walls are nitrided by introducing nitrogen into the heat treatment furnace while the temperature of the hydrogen-etching heat treatment decreases, thereby forming a SiN film along the inner walls. Next, an HTO film is formed, as gate insulating films, on the SiN film along the inner walls of the trenches. Thereafter, by PDA, an oxygen amount of an interface section of a SiO2/SiC interface is set to be at most 1.6×1015/cm2 and a nitrogen amount is set to more than 5.0×1014/cm2.

Abstract: A method for fabricating a semiconductor wafer is provided, where the semiconductor wafer includes a diamond layer and a semiconductor layer having III-Nitride compounds. The method includes the steps of: disposing a nucleation layer on a SiC substrate and disposing at least one semiconductor layer on the nucleation layer, the at least one semiconductor layer including a III-Nitride compound. The method further includes the steps of: disposing a protection layer on the at least one semiconductor layer; bonding a carrier wafer to the protection layer, the carrier wafer including a SiC substrate; removing the substrate, the nucleation layer and a portion of the at least one semiconductor layer; disposing a diamond layer on the at least one semiconductor layer; depositing a substrate wafer on the diamond layer; and removing the carrier wafer and the protection layer.

Abstract: The method of etching a boron-doped p-type silicon wafer includes preparing an etching gas by introducing an ozone-containing gas and hydrofluoric acid mist into a chamber and mixing them; and performing gas phase decomposition of a surface layer area of a boron-doped p-type silicon wafer with a resistivity of 0.016 ?cm or less by bringing the etching gas into contact with a surface of the boron-doped p-type silicon wafer; and further includes introducing the ozone-containing gas into the chamber at a flow rate of 3,000 sccm or more; and preparing the hydrofluoric acid mist by atomizing hydrofluoric acid with a hydrofluoric acid concentration of 41 mass % or more.

Abstract: A film forming method forms a silicon film on a substrate placed on a turntable which rotates and passes through first and second process regions that are mutually separated along a circumferential direction inside a vacuum chamber that is settable to a first temperature at which Si—H bond dissociation can occur. A film forming process includes forming a molecular layer of SiH3 on the substrate, by supplying a Si2H6 gas that is set to a second temperature higher than the first temperature during a time period in which the substrate passes through the first process region, and forming a molecular layer of SiCl3 on the substrate having the molecular layer of SiH3 formed thereon while causing the Si—H bond dissociation in the molecular layer of SiH3, by supplying a gas including silicon and chlorine during a time period in which the substrate passes through the second process region.

Abstract: Epitaxially coated semiconductor wafers of monocrystalline silicon comprise a p+-doped substrate wafer and a p-doped epitaxial layer of monocrystalline silicon which covers an upper side face of the substrate wafer; an oxygen concentration of the substrate wafer of not less than 5.3×1017 atoms/cm3 and not more than 6.0×1017 atoms/cm3; a resistivity of the substrate wafer of not less than 5 m?cm and not more than 10 m?cm; and the potential of the substrate wafer to form BMDs as a result of a heat treatment of the epitaxially coated semiconductor wafer, where a high density of BMDs has a maximum close to the surface of the substrate wafer.

Abstract: An enhancement mode Group III nitride-based transistor device includes a body having a first surface and a Group III nitride barrier layer arranged on a Group III nitride channel layer and forming a heterojunction therebetween. A first cell field includes transistor cells and an edge region. Each transistor cell includes source, gate and drain fingers extending substantially parallel to one another on the first surface in a longitudinal direction. The gate finger, arranged laterally between the source and drain fingers, includes a p-doped Group III nitride finger arranged between a metallic gate finger and the first surface. The edge region surrounds the transistor cells and includes an edge termination structure having an isolation ring and a p-doped Group III nitride runner. The isolation ring locally interrupts the heterojunction. The runner, extending transversely to the longitudinal direction, is located laterally between the isolation ring and an end of the drain finger.

Abstract: A film forming method includes forming a cancel layer on a substrate, which is disposed within a processing container and on which a base film is formed, in a pressure-reduced atmosphere, the cancel layer cancelling orientation of the base film, forming an initial metal film by supplying a metal material gas and a boron-containing gas to the substrate on which the cancel layer is formed, and forming a main metal film on the substrate on which the initial metal film is formed.

Abstract: In a method for producing a buried cavity in a semiconductor substrate, trenches are produced in a surface of a semiconductor substrate down to a depth that is greater than cross-sectional dimensions of the respective trench in a cross section perpendicular to the depth, wherein a protective layer is formed on sidewalls of the trenches. Isotropic etching through bottom regions of the trenches is carried out. After carrying out the isotropic etching, the enlarged trenches are closed by applying a semiconductor epitaxial layer to the surface of the semiconductor substrate.

Abstract: A method for manufacturing a mixed substrate having, on a main face of a support substrate, a first region and a second region, includes a) providing a starting substrate which comprises an intermediate layer, consisting of the second material, and the support substrate; b) forming a mask which comprises an aperture delimiting the first region; c) forming a cavity; and d) forming the first region by epitaxially growing the first material in a single crystal form in the cavity The method includes step c1), performed before step d), of forming a protective layer, made of an amorphous material, overlaying the flank of the cavity and leaving the bottom of said cavity exposed to the external environment.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.