Abstract: Provided is a method of manufacturing a magnetic tunnel junction that simultaneously realizes removal of oxides on side walls of a magnetic layer and formation of a protective film and prevents deterioration of magnetic characteristics. The method includes: a first step 802 of etching a stacked film including a first magnetic layer, a MgO barrier layer, and a second magnetic layer stacked in order by plasma etching using an oxidizing gas to form the magnetic tunnel junction; and a second step 803 of simultaneously introducing an organic acid gas which is an n-valent acid and a precursor gas having a corresponding metal element valence of m, to form a first protective film on side walls of the magnetic tunnel junction. In the second step, the precursor gas is introduced at a molar ratio of n/m or more with respect to 1 mole of the organic acid gas introduced.

Abstract: Disclosed herein are optical elements and methods for making the same. Such optical elements may comprise a first layer disposed on a substrate, a second layer disposed on the first layer, a terminal layer disposed on the second layer, and a cap layer disposed on the terminal layer. The cap layer may comprise boron, boron nitride, or boron carbide. Such optical elements may be made using a method comprising depositing a first layer using vapor deposition such that the first layer is disposed on a substrate, depositing a second layer using vapor deposition such that the second layer is disposed on the first layer, depositing a terminal layer using vapor deposition such that the terminal layer is disposed on the second layer, and depositing a cap layer comprising boron, boron nitride, or boron carbide using vapor deposition such that the cap layer is disposed on the terminal layer.

Abstract: There is provided an organic light emitting diode display device. The organic light emitting diode display device includes a substrate divided into an emission area and a non-emission area, an overcoating layer disposed on the substrate and including a plurality of micro lenses, a plurality of first electrode patterns disposed on the overcoating layer and spaced away from each other in the emission area, an organic emission layer disposed on the plurality of first electrodes, and a second electrode disposed on the organic emission layer.

Abstract: A semiconductor device includes: a base plate having a heat dissipation surface and a mounting surface opposite to each other; a semiconductor chip mounted on the mounting surface of the base plate; a sealing material sealing the semiconductor chip; a first sheet adhering to the heat dissipation surface of the base plate and having plural openings; and a second sheet covering the first sheet.

Abstract: A method of fabricating a semiconductor package includes preparing a panel package including a redistribution substrate, a connection substrate and a plurality of lower semiconductor chips; sawing the panel package to form a plurality of separated strip packages each of which includes the sawed redistribution substrate, at least two of the lower semiconductor chips, and the sawed connection substrate; and providing a plurality of upper semiconductor chips on one of the strip packages to electrically connect the upper semiconductor chips to the sawed connection substrate.

Abstract: The disclosure includes forming a SiGe region on two adjacent fin structures and a SiP region on the fin structures adjacent to the SiGe region; forming SDB trenches; forming SiN plugs over the SDB trenches to make top-sealed hollow SDB trenches. The process for forming SDB trenches adds no additional cost, and the process is compatible with existing process flow. The SiN plugs are configured to seal the SDB trenches from top, such that the SDB trenches are filled with air and do not need to be thermally annealed. The advantage includes low fin loss in the annealing oxidation process and better controlled uniformity of the SDB trenches. Air in the SDB trenches reduces the parasitic capacitance of adjacent contacts, therefore and it is conducive to improving the device speed.

Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3 and a carbon concentration at the first position is equal to or less than 1×1018 cm3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm?3.

Abstract: A method for p-type doping of a silicon carbide layer includes first implantation step of implanting aluminum dopants into a preselected region of the silicon carbide layer by ion implantation, an annealing step of annealing the silicon carbide layer after performing the first implantation step, a second implantation step of implanting beryllium dopants into the preselected region by ion implantation before the annealing step. A ratio of the total aluminum dose in the first implantation step to the total beryllium dose in the second implantation step is in a range between 0.1 and 10.

Abstract: The present application discloses an array substrate and a display panel. The array substrate includes an underlying substrate and a first color resist layer. The first color resist layer is formed on the underlying substrate to block a channel region. The first color resist layer has at least two color resist layers, and the two color resist layers correspond to different colors and are disposed in a stack-up manner.

Abstract: A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 1018-1022 cm?3. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under N2 pressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).

Abstract: A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.

Abstract: Disclosed is a Schottky barrier diode which may be applied to an application that requires a low off current (Ioff), such as a mobile integrated circuit. The Schottky barrier diode can improve a blocking characteristic for a backward current flow while maintaining an advantage of a turn-on current, by improving the structure of a contact surface that is pinched off by depletion.

Abstract: A semiconductor device includes: a drift layer of a first conductivity type which is made of silicon carbide; a junction region formed on one main surface of the drift layer; a junction termination extended region of the drift layer, the junction termination extended region being formed outside the junction region when the one main surface is viewed in plan view, and the junction termination extended region containing an impurity of a second conductivity type opposite to the first conductivity type; and a guard ring region of the drift layer, the guard ring region being formed at a position overlapping the junction termination extended region when the one main surface is viewed in plan view, and the guard ring region containing the impurity of the second conductivity type with a concentration that is higher than that of the junction termination extended region, wherein in the junction termination extended region, the concentration of the impurity of the second conductivity type in a depth direction from the o

Abstract: A method for forming a semiconductor device is disclosed. The method for forming the semiconductor device includes forming a first sacrificial film over a target layer to be etched, forming a first partition mask over the first sacrificial film, forming a first sacrificial film pattern by etching the first sacrificial film using the first partition mask, forming a first spacer at a sidewall of the first sacrificial film pattern, and forming a first spacer pattern by removing the first sacrificial film pattern. The first partition mask includes a plurality of first line-shaped space patterns extending in a first direction. A width of at least one space pattern located at both edges from among the plurality of first space patterns is smaller than a width of each of other space patterns.

Abstract: Provided is a method of evaluating a silicon layer, including forming an oxide film on a surface of a silicon layer, performing a charging treatment of charging a surface of the formed oxide film to a negative charge, and measuring a resistivity of the silicon layer that has been subjected to the charging treatment by a van der Pauw method.

Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a semiconductor fin and a liner in contact with end portions of the semiconductor fin. A first source/drain contacts the liner and sidewalls of the semiconductor fin. A gate structure is in contact with and surrounds the semiconductor fin. A second source/drain is formed above the first source/drain. The method includes forming, on a substrate, at least one semiconductor fin having a first spacer in contact with an upper portion of the semiconductor fin, and a second spacer in contact with the first spacer and a lower portion of the semiconductor fin. The semiconductor fin is patterned into a plurality of semiconductor fins. A liner is formed on exposed end portions of each semiconductor fin of the plurality of semiconductor fins.

Abstract: Methods of fabricating a field-effect transistor, where the methods include providing a substrate, forming a first well of a first doping polarity type in the substrate, and forming a gate on a portion of the first well, the gate comprising an oxide layer and an at least partially conductive layer on the oxide layer. A second well of a second doping polarity type is formed by implanting ions in the first well, the second well extending under a portion of the gate. A first one of a source and drain of the first doping polarity type in or on the second well is formed, thereby defining a channel of the transistor under the gate. A second one of the source and drain of the first doping polarity type in or on the first well is formed. The second well may be formed by means of a two-step implant.

Abstract: A heating apparatus, a method and a system for producing semiconductor chips in a wafer assembly are disclosed. In an embodiment a heating device includes a heating plane configured to be arranged parallel to a plane of the semiconductor chips in the wafer composite and a first heating unit extending substantially in a radial direction with respect to a reference point in the heating plane, wherein the first heating unit includes a plurality of inductive heating elements arranged adjacent to each other in a substantially radial direction, each inductive heating element having a predetermined distance from the reference point, and wherein the inductive heating elements are formed as electromagnets or permanent magnets configured to generate eddy currents in a carrier of the wafer composite.

Abstract: A method of forming a semiconductor device includes forming, on a lower structure, a mold structure having interlayer insulating layers and gate layers alternately and repeatedly stacked. Each of the gate layers is formed of a first layer, a second layer, and a third layer sequentially stacked. The first and third layers include a first material, and the second layer includes a second material having an etch selectivity different from an etch selectivity of the first material. A hole formed to pass through the mold structure exposes side surfaces of the interlayer insulating layers and side surfaces of the gate layers. Gate layers exposed by the hole are etched, with an etching speed of the second material differing from an etching speed of the first material, to create recessed regions.

Abstract: A method of manufacturing array substrate and a display panel, wherein, the method of manufacturing array substrate includes: depositing a gate electrode, a gate insulation layer, a semiconductor layer, a metal layer and a photoresist; forming an non-exposure area, a partial exposure area and a full exposure area through exposure and developing; then, performing a first ashing treatment and a wet etching to form a metal layer recess, and performing a second ashing treatment to etch off residual photoresist which remains in the metal layer recess after the first ashing treatment; and finally performing a dry etching to form a pattern of a channel region.