Abstract: A rack equipment management system and method for providing a convenient and efficient manner to automatically manage rack equipment associated with information processing based upon power consumption and heat dissipation policies is presented. In one embodiment of the present invention, a rack equipment management system includes a rack equipment management policy data store, a management component, and a communication bus. The rack equipment management policy data store stores policy information related to rack equipment operations. The management component manages power consumption and thermal load of the rack equipment. The communication bus communicatively couples the rack equipment management policy data store and the management component.

Abstract: An apparatus and method for controlling CPU speed transition can use an SMI (System Management Interrupt) signal to perform speed transition of a CPU of a computer such as a notebook computer. However, if the bus master device is in the active state, a control operation needed for CPU speed transition is cancelled at the same time an event signal (e.g., a watchdog SMI or an embedded controller SMI) is created at prescribed intervals and the bus mater device active state is accordingly re-checked. Therefore, when the bus master device is in the active state, the control operation for CPU speed transition is cancelled to prevent the computer from hanging up, and the CPU speed transition control operation is periodically retried to increase a likelihood of a normal CPU speed transition or the normal CPU speed transition can be established.

Abstract: A method of reducing the power consumption of microprocessor system is provided, wherein: said microprocessor system comprises a microprocessor (2) and a memory (4) connected by a bus (6); said memory (4) contains a plurality of data values, each represented by a number of bits, for transmission to said microprocessor (2) via the bus (6); and at least some of said data values contain unused bits; and wherein said method includes assigning values to said unused bits in such a way as to reduce the Hamming distance between successive data values by a greater extent than setting all of said unused bits to an arbitrary predetermined value.

Abstract: Methods and systems are disclosed for power usage level management of blades installed in blade servers. When a new blade added is to a blade server, possible power usage levels for the new blade are assessed to determine possible effects on the total power usage level of the chassis. By assessing the different power usage levels, the chassis controller can then make intelligent decisions as to the power usage levels at which new blades will be allowed to operate while still keeping within chassis power supply capabilities. Blade power usage levels can be based upon a variety of considerations, including processor performance modes and blade configuration options.

Abstract: A method and apparatus for managing processor availability uses a disabling microcode patch to prevent unauthorized processor(s) usage. By loading the disabling microcode to one or more processors that are not authorized to be in operation (e.g., not currently licensed, etc.) the OS can not circumvent the disablement.

Abstract: The present invention provides a method and apparatus for updating serial devices. The apparatus includes a plurality of serial registers. The apparatus further includes a device adapted to provide a signal and a plurality of parallel registers, wherein each of the parallel registers is adapted to access at least one of the plurality of serial registers at substantially the same time in response to detecting the signal.

Abstract: A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

Abstract: A personal computer (PC) adapted to function as a personal digital assistant (PDA) includes: a central processing unit (CPU) responsive to a control signal to load a first operating system or a second operating system, wherein the first operating system is run by the PC in a first PC mode and the second operating system is run by the PC in a second PDA mode. A method of operating a personal computer (PC) in either a PC mode or a PDA mode is also provided that includes: initiating a control signal; and loading a first or second operating system based on the control signal, wherein the first operating system operates the PC is the first PC mode and the second operating system operates the PC is the second PDA mode.

Abstract: A system, apparatus, and method for depicting and responding to systematic problems and/or incidents in computing devices at a Basic Input/Output System level are described herein.

Abstract: Provided is a method, system, an program for power management of storage units in a storage array. A power profile is accessed for a storage array including a plurality of storage units, wherein each storage unit is enabled to operate in one of a plurality of power consumption modes, and wherein the power profile indicates a power mode specifying a power consumption mode. Data is migrated from at least one storage unit to at least one storage unit designated as an active storage unit consuming power in an active power consumption mode. The power consumption mode of at least one storage unit not designated as active is altered to the specified power consumption mode indicated in the accessed profile, wherein the specified power consumption mode consumes less power than the active power consumption mode.

Abstract: An information device has a storage medium storing information items which includes a first program provided on a first partition, a second program and data provided on a second partition to restore the first program on the first partition to a predetermined state, a boot block which causes system activation from one of the first partition and the second partition, and an active-partition switching program which indicates, to the boot block, one of the first and second partitions. An input/output system activates the active-partition switching program when a specific operation is performed. The active-partition switching program indicates to the boot block that system activation is to be executed from the second partition.

Abstract: The detector includes the plug for connecting the personal computer through a cable, battery power supply which provides a constant power supply, and the MCU which receives a specific potential from the personal computer when the later is connected.

Abstract: The present invention is directed to a method and apparatus of automatic power management control for a Serial ATA interface that utilizes a combination of IOP control and specialized hardware control. The method may include steps as follows. It is determined, preferably based on a value of the Automate bit in a Task File Ram of a Serial ATA interface, whether a Serial ATA device of the Serial ATA interface is being controlled via the IOP or controlled by the specialized Serial ATA automation hardware. When the Serial ATA device is controlled via the IOP, the IOP may decide when to power up/down the Serial ATA interface. When the Serial ATA device is controlled by the specialized Serial ATA automation hardware, the method may proceed as follows. An idle or active condition of a Serial ATA interface utilizing a combination of IOP control and specialized hardware control is then automatically detected.

Abstract: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.

Abstract: Disclosed is a program product for directing the information processing apparatus to control an execution mode of a central processing unit(CPU) provided, the CPU having a plurality of execution modes, whose types and power consumptions of executable processing are different from one another, the program product comprising: an apparatus readable medium; recovery time acquisition means for acquiring a recovery time which is a time required for the CPU to recover from a low power mode to a high power mode of which power consumption is higher than that of the low power mode; allowed time acquisition means for acquiring the longest allowed time from a request for processing unprocessable in the low power mode and processable in the high power mode to a start of the processing after the CPU recovers to the high power mode, the request being made by an input/output device; and execution mode setting means for settingthe CPU in a state of being shiftable to the low power mode if it is determined that the CPU is able

Abstract: A system for generating, delivering and distributing electrical power to network elements over a data communication network infrastructure within a building, campus or enterprise. Consolidating power distribution and data communications over a single network simplifies and reduces the cost of network element installation and provides a means of supplying uninterrupted or backup power to critical network devices in the event of a power failure. The invention includes power/data combiners that combine a data communication signal with a low frequency power signal. The combined signal is transported over the LAN infrastructure where a power/data splitter extracts the data signal and the power signal and generates two separate outputs. The power over LAN system of the present invention operates with high bandwidth data communication networks, i.e., 10 Mbps, 100 Mbps, 1000 Mbps.

Abstract: One or more processors are activated and deactivated responsive to processing activity in order to meet a performance or response requirement. Hardware facilities or software modules monitor workload. A policy manager receiving workload information determines processor number based on a predetermined performance criteria. A resource pool module selects which processors are activated and deactivated in response to changes in the determined processor number as determined by the policy manager. The resource pool module prepares a selected processor for deactivation by migrating any processes or thread running thereon to other processor(s) in the pool of available processors and by flushing the contents of the selected processor's cache memory. A CPU power control module transitions a processor selected for deactivation from a full power state to a low-power state.

Abstract: One of the ground pins on a conventional floppy drive host connector is coupled to an input of a computer system and to a supply potential via a pull-up resistor. When a floppy drive is connected to the floppy drive host connector, the pin is pulled to ground by virtue of the ground connections within the floppy drive device. When a floppy drive is not connected to the floppy drive host connector, the pin remains at the supply potential. BIOS firmware or another system within the computer may detect the presence of the floppy drive by simply reading the value of the input.

Abstract: An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

Abstract: A system and method of booting an embedded system having a processor, nonvolatile memory and a remote media interface connected to the processor. Boot code is executed within the nonvolatile memory. The processor determines if a storage device is connected to the remote media interface and, if a storage device is connected to the remote media interface, program code loaded from the storage device to the processor is executed.