Abstract: A system and method for remote power control across multiple distinct nodes of a logically coherent data processing system where each node has the design of a traditional standalone SMP server. The system is partitioned into two or more static partitions. Remote power control for the partition is achieved using a modified wake-on-LAN implementation in which magic packet filters on each NIC in the partition are modified to enable remote, partition-wide restart by a magic packet that is recognized by or common to all of the nodes. In one embodiment the wake-on-LAN filters of each NIC in the partition recognize and respond to magic packets addressed to any of the NIC's in the partition. In another embodiment, the wake-on-LAN filters of each NIC in the partition are modified to respond to a universal magic packet.

Abstract: A data transfer control device includes an OUT-transfer transmitter circuit which transmits OUT data by driving a serial signal line, a clock-transfer transmitter circuit which transmits a clock signal CLK by driving a serial signal line, a PLL circuit which generates the clock signal CLK, and a power-down setting circuit which sets a power-down mode. In a first power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode, and the clock-transfer transmitter circuit is set to the power-down mode to stop a system clock signal of a target-side data transfer control device. In a second power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode without setting the clock-transfer transmitter circuit to the power-down mode.

Abstract: A system and method of processor type determination. A reset vector from a processor is identified. Responsive to characteristics of the reset vector, a processor type of the processor is determined.

Abstract: Improved approaches for enabling user accounts to be portable across different multi-user computer systems are disclosed. A user account created at a multi-user computer can be stored to an external, portable data store, thereby rendering the user account portable. The multi-user computer system, e.g., through its operating system, locates user accounts on not only in local storage of the multi-user computer system, but also in any removable data storage attached to the multi-user computer system. Hence, by coupling the external, portable data store to another multi-user computer, a user is able to login to any supporting multi-user computer and be presented with their user configuration and user directory. Since the data store that stores the user account is not only external but also portable, a user can simply tote the data store to the location of different multi-user computers.

Abstract: A method and apparatus for notifying an end user of a powered device on an Ethernet based network that the powered device will not be reliably powered due to an excess demand condition comprising: detecting an attached powered device; identifying the class of the attached powered device, the class comprising the power requirements of the attached powered device; identifying an excess demand condition; and temporarily supplying power to the attached powered device for a time interval thereby notifying an end user that the powered device is not being reliably powered because of an excess demand condition.

Abstract: Disclosed are, inter alia, instantaneously restartable clocks and their use. For example, instantaneously restartable clocks can be used to receive data from another independently clocked subsystem in a manner that removes the possibility of metastability errors. A restartable clocking signal generator, relying on oscillating signals typically generated by a continuous oscillating source, is used to generate a restartable clocking signal which can be asynchronously restarted in response to one or more control signals. In one implementation, an apparatus includes multiple independently clocked subsystems and a clockless sequencing network, with the clockless sequencing network being used to initiate the start of a restartable clock in order to reliably receive and process data between the independently clocked subsystems.

Abstract: A system, method and kit for forming a powered communications interface in a computer system having a computer housing. A processor, a power supply and a communications interface are installed in the computer housing. The power supply includes a ground rail, a first power rail having a first nominal voltage and a second power rail having a second nominal voltage. The processor is connected to the power supply and the communications interface. A booster is connected to the first power rail and is used to boost power from the first power rail to a third nominal voltage and to place the third nominal voltage on a third power rail. An externally accessible connector having a ground conductor and first, second and third power conductors is connected to the booster and the power supplies such that, wherein the first conductor is connected to the first power rail, the second conductor is connected to the second power rail and the third conductor is connected to the third power rail.

Abstract: The power consumption is lowered in an apparatus equipped with memories. Assuming that memories are, for example, of DRAM type, each usage circumstance of DRAM modules on a chip is observed by an observation circuit and a power supply control signal is made to be generated by a CPU in order to turn off the power supply to the DRAM modules actually in a vacant condition, in a disused condition or in an unnecessary condition according to that circumstance observed result. It becomes possible to lower the power consumption as a whole apparatus by turning off only DRAM modules in a disused condition and the like according to the power supply control signal in the power supply on/off circuit.

Abstract: A method and related apparatuses provide a virtual runtime interface for modifying basic input/output system (BIOS) settings. A processing system may provide the virtual runtime interface after the processing system has booted an operating system (OS). User input that specifies a modified BIOS setting may be received through the virtual runtime interface. To provide the virtual runtime interface, the system may transition from an OS context to a system management mode (SMM) context, and may determine whether the amount of time spent in the SMM context approaches an SMM time limit. If the amount of time spent in the SMM context approaches the SMM time limit, the system may automatically transition from the SMM context back to the OS context. Other embodiments are described and claimed.

Abstract: Network architecture, computer system and/or server, circuit, device, apparatus, method, and computer program and control mechanism for managing power consumption and workload in computer system and data and information servers. Further provides power and energy consumption and workload management and control systems and architectures for high-density and modular multi-server computer systems that maintain performance while conserving energy and method for power management and workload management. Dynamic server power management and optional dynamic workload management for multi-server environments is provided by aspects of the invention. Modular network devices and integrated server system, including modular servers, management units, switches and switching fabrics, modular power supplies and modular fans and a special backplane architecture are provided as well as dynamically reconfigurable multi-purpose modules and servers.

Abstract: A method and apparatus for significantly reducing the number and types of non-volatile memory used on a typical motherboard is disclosed. While there are typically three or more types of non-volatile memory used to support the CPU during system boot and initialization, the present invention uses only one. This allows for a significant savings in materials cost and design effort.

Abstract: A system for addressing bus components comprises a bus controller component that controls access between a CPU and a memory address space. A plurality of bus components connected to said bus controller over a bus are addressable via a memory mapped address within the address space. An address translation table is stored on at least one of the plurality of bus components. The bus translation table stores a translation between a virtual address and a real address.

Abstract: A maintenance terminal for a disk array device is provided which can make setting of the disk array device and can easily confirm the setting contents. The maintenance terminal for the disk array device has three jumper connectors as setting terminals into which a conduction pin is inserted. The maintenance terminal also has eight light emitting diodes disposed in two rows and being capable of turning on and off in correspondence with a setting state of the disk array device in a network selectively changed through insertion of the conduction pin into the setting terminals.

Abstract: A programmable synchronizer system for effectuating data transfer across a clock boundary between a core clock domain and a bus clock domain, wherein the core clock domain is operable with a core clock signal and the bus clock domain is operable with a bus clock signal, the core and bus clock signals having a ratio of N core clock cycles to M bus clock cycles, where N/M?1. A first synchronizer is provided for synchronizing data transfer from a core clock domain logic block to a bus clock domain logic block. A second synchronizer is operable to synchronize data transfer from the bus clock domain logic block to the core clock domain logic block. Control means are included for controlling the first and second synchronizers, the control means operating responsive at least in part to configuration means that is configurable based on skew tolerance and latency parameters.

Abstract: A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a reference clock, using PL circuits in such a way that the clocks have sufficient S/N ratios in spite of the S/N ratio limitation by the noise floor. A first reference frequency clock is supplied to a first PLL circuit to generate an intermediate-frequency clock having an intermediate frequency having a predetermined ratio to the reference clock. The intermediate-frequency clock is supplied to a second and a third PLL circuits to generate a second and a third reference frequency clocks having frequencies respectively having a second and a third ratios to the intermediate frequency, respectively.

Abstract: A system and method to initialize registers with an EEPROM stored boot sequence is described. The method includes reading configuration records from an EEPROM coupled to an ASIC upon system reset. The configuration records specify target configuration registers and data to be written to the registers. The configuration records are translated to register write requests and data is written to the target registers via a bus of the ASIC to initialize the registers. Other masters, such as a processor, may be blocked from accessing the registers during the initialization.

Abstract: A data processing network includes a set of servers, at least one switch module to interconnect the servers, and a management module. The management module consults power state information stored in the network following a power transition and restores power to at least some of the servers and switch modules based on the power state information. The power state information prevents the management module from restoring power to servers and switch modules having incompatible communication protocols. In one embodiment, the plurality of servers and the switch modules are hot-swappable modules that are all inserted into a single chassis. In this embodiment, the server modules and at least one switch module share selected resources of the network including system power. The switch modules and servers may employ Ethernet, fiber channel, optical, and serial communication protocols.

Abstract: An accessor moveably disposed within a data storage and retrieval system, where that accessor includes an information input/output device and a power supply connector disposed on a gripper mechanism such that the information input/output device and the power supply connector can be releaseably coupled/connected to an information input/output port and a power port, respectively, disposed on a hard disk drive unit disposed in a storage slot within the data storage and retrieval system. A data storage and retrieval system which includes one or more of Applicants' accessors, one or more hard disk disposed in one or more hard disk drive units each of which includes an information input/output port in communication with that hard disk, and an information transfer station in communication with a host computer, wherein that information transfer station can communicate with Applicants' accessor(s).

Abstract: An Infiniband device can be provided. The device can comprise an input port having a serialiser/deserialiser. The serialiser/deserialiser can comprise: a data buffer for storing data from a received serial data stream and for outputting the stored data in parallel groups and a code detector for detecting a predetermined code pattern in the serial data stream and generating a code detection output in response thereto. The serialiser/deserialiser can also comprise a transition detector for detecting transitions in the serial data stream and reconstructing a serial data clock therefrom, and for generating a plurality of parallel data clocks from the serial data clock, each parallel data clock having a different phase. The data buffer can be responsive to the code detection output to adjust a parallel data group start position within the serial data stream and to cause a selection of one of the reduced frequency clocks having a phase corresponding to the adjusted parallel data group start position.

Abstract: An embedded processor system including at least one gated power unit including an internal ROM and a power controller that provides one or more gated power signals to selectively provide power to each gated power unit. The power controller provides a gated clock signal to the embedded processor to selectively control power consumption of the processor. The power controller powers down each gated power unit after freezing the processor and then powers up each gated power unit before reactivating the processor. The embedded processor system may include isolation circuitry, such as clamp circuitry or the like, that is operative to minimize current flow into each gated power unit when powered down. The gated power units may include a static function. The ROM of an embedded ROM-based microprocessor system is powered down when the microprocessor is idle to reduce or otherwise eliminate intrinsic leakage.