Abstract: A static memory device is disclosed having an array of static memory cells, each memory cell having first and second cross-coupled inverters. All of the memory cells have distinct power voltage connections to the first and second inverters of each memory cell. When a reset signal occurs, the device's reset apparatus generates a voltage imbalance on the power voltage connections so that distinct voltage levels are applied to the first and second cross-coupled inverters of each memory cell. The voltage imbalance causes all of the memory cells in the array to be set into a predetermined state. In a preferred embodiment, the power voltage connections include a common high voltage power connection to all of the memory cells and distinct low voltage power connections to the first and second inverters of each memory cell.

Abstract: A CMOS read-only memory with static operation having at least one individually activatable row (R.sub.n) and a plurality of main columns (C.sub.1, C.sub.2) which cross the rows, each crossing including pull-down cell (N.sub.1) corresponding to a logical "0" or a pull-down cell (N.sub.2) corresponding to a logical "1", the pull down cells controlled the individually activatable row, the main columns leading to the supply voltage through a respective pull-up transistor (P.sub.1, P.sub.2). To each main column, there is an associated auxiliary column (CX.sub.1, CX.sub.2) which is also connected to the supply voltage through a respective pull-up transistor (PX.sub.1, PX.sub.2). The gates of the pull-up transistors of the main columns are connected to a respective auxiliary column, and the gates of the pull-up transistors of the auxiliary columns are connected to a respective main column.

Abstract: A static random access memory has a multiplicity of separate memory blocks, only one of which is activated during each memory access cycle. Each memory block has its own separate bit line equalization circuity which equalizes the voltages of each complementary bit line pair in the memory block. A write equalization decoder automatically, at the end of each write cycle, generates a decoded write recovery equalization pulse, which activates the bit line equalization circuitry only in the memory block to which data has been written. As a result, the process of equalizing the bit lines is removed from the critical timing path for accessing the memory after a write cycle, eliminating one of the primary problems associated with the use of address transition detection in static memory devices. In addition, the write recovery equalization pulse can be generated at high speed because the decoded write recovery equalization pulse drives only one of the multiplicity of separate memory blocks.

Abstract: In a magnetic memory device for use in selectively carrying out a write-in operation and a readout operation of a pair of vertical Bloch lines as an information carrier in a domain wall of a stripe domain extended along a longitudinal direction, a deflected in-plane magnetic field is applied to an end portion of the stripe domain and deflected relative to the longitudinal direction at an angle within an angle range by the use of a pair of magnetic units. The deflected in-plane magnetic field serves to stably hold a single Bloch line to a predetermined flank wall of the stripe domain during the write-in operation or to stably separate three Bloch lines from one another during the readout operation. Such application of the deflected in-plane magnetic field also serves to smoothly propagate each Bloch line.

Abstract: A divided bit line type dynamic semiconductor memory device comprises parallel main bit line pairs, divided bit line pairs provided at each main bit line pair, parallel word lines insulatively crossing the divided bit line pairs, and memory cells provided at the cross points between the divided bit line pairs and the word lines. First sense amplifiers are coupled to the divided bit line pairs. Second sense amplifiers are coupled to the main bit line pairs. First transfer gate sections are coupled between the divided bit line pairs and the main bit line pairs, respectively. Second transfer gate sections are coupled between the main bit line pairs and the second sense amplifier circuits, respectively.

Abstract: A magneto-optical memory medium of a laminar structure comprising at least one non-magnetic layer, and a plurality of magneto-optical storage layers separated from each other by corresponding non-magnetic layers, and wherein information is read out from a selected one of the storage layers by detecting a change in the Kerr rotation angle of a corresponding one of light beams of different wavelengths applied to the memory medium, which change depends upon magneto-optical anisotropy of the storage layers. A thickness of one of the storage layers is determined so that the change in the Kerr rotation angle of each of the light beams repesents the anisotropy of the corresponding storage layer, irrespective of the anisotropy of the other storage layers. Also disclosed is a magneto-optical apparatus for writing and/or reading information on or from the desired magneto-optical layers.

Abstract: A component metallization interconnection system in a monolithic integrated circuit system for providing electrical interconnections between circuit components and for providing magnetic interaction regions for information storage.

Abstract: A dynamic random access memory comprises memory cells (MA1-Man) and sense amplifies (SA1-SAn) in a memory array region III and memory cells (MB1-MBn) and sense amplifies (SB1-SBn) in a memory array region IV. In reading operation, first, the sense amplifiers in one region comprising a memory cell designated by an address signal are activated and then sense amplifiers in the other region are activated. As a result, since amplifying operation by the sense amplifiers is performed sequentially, a peak value of a current consumed by the amplification can be reduced.

Abstract: An improved magnetic bubble memory device includes a continuous propagator overlay on a sheet of magnetic material. The propagator overlay being adapted to reduce the statistical switching effects and overall coercivity of the propagator overlay. The propagator overlay consists of multiple layers of soft magnetic material being alternately arranged with non-magnetic material, in a geometric pattern specified so as to produce domain walls only internal to the pattern boundary, the soft magnetic material being chosen for its initial low coercivity characteristics and having characteristics approaching zero magneto-striction.

Abstract: The rate of single event upset in a memory cell is reduced by a pair of active devices in the cross-coupling between a pair of inverters. The active devices are controlled by voltages internal to the memory cell such that writing into the cell is not slowed significantly.

Abstract: Magnetic bubble memory in hybrid technology using rows of chevron patterns. The memory detection system has an active detection zone (4) constituted by rows of chevrons, in order to stretch into the form of a strip the bubbles from a propagation path (2), and a first detector (8); a bubble elimination zone (12) constituted by forcing back means (18) for stopping the advance of the bubbles and for forcing them outside the detection system; and a passive detection zone (6) located following the bubble elimination zone (12) and incorporating a second detector (9), to which no bubble must be exposed, in order to eliminate the unwanted signal due to the influence of a rotary magnetic field necessary for the propagation of the bubbles. According to the invention, elimination zone (12) is provided with at least one barrier (20) produced by ion implantation in order to block the passage of the bubbles from active zone (4) to passive zone (6).

Abstract: In a nonvolatile semiconductor memory according to the invention, a power source voltage of 5 V used in an ordinary read mode is applied to a read line in the data read mode without changing its value. If a write line, a selection gate line, a control gate line, and a read line are respectively set at 0 V, 5 V, 0 V, and 5 V in the data read mode, the potential at an n-type diffusion layer becomes 0 V. In this case, the potential at the control gate line is 0 V, and the potential at a floating gate electrode becomes substantially 0 V. That is, an electric field is not applied to a thin insulating film located between the floating gate electrode and the n-type diffusion layer. As a result, electron injection and discharge due to the tunnel effect do not occur.

Abstract: Single event upset hardening is provided in a static random access memory cell, including cross-coupled inverters, by the restoration of voltages at selected nodes within the cell by a pair of transistors connected to the cross-coupling between inverters.

Abstract: A complementary MOS one-capacitor dynamic RAM cell which operates with a non-boosted wordline without a threshold loss problem and which includes one storage capacitor and n- and p-type transfer devices connected to the storage capacitor which function as two complementary transistor devices having gates controlled by complementary signals on the RAM wordlines.

Abstract: A C-MOS semiconductor memory circuit includes a read amplifier and a tristate bus driver. The read amplifier is a two stage amplifier. The bit lines in the memory are connected via P-MOS pull-up transistors to the supply voltage. The logic low level is 1 Volt below the supply voltage. In order to bring the input signals for the difference amplifier at a most sensitive and fast level, a d.c.-shifting amplifier of the "emitter follower" type is connected between each input thereof and the associated bit line. The difference amplifier and the two follower amplifiers are activated only for a short period of time by means of a selection signal which gives a strong restriction in the power dissipation. The tristate driver comprises a push-pull output stage and an inverting AND gate which is controlled by the output of a difference amplifier and by an equalization signal which is also applied to the difference amplifier and therefore is of a simple design and gives only a low signal delay.

Abstract: A bipolar/CMOS read/write control and sensing circuit is provided for use with MOS memory cells in which data can be written into and sensed in the memory cells at high speeds. The MOS memory cell is coupled with a word line and between first and second bit lines at corresponding first and second sense nodes. The control and sensing circuit includes a bit-line clamping network which is responsive to an output control signal for clamping the first and second bit lines during a read operation so as to present a low impedance thereby decreasing the read time and for unclamping of the first and second bit lines during a write operation so as to present a high impedance which reduces the write time.

Abstract: In order to reduce the down time of a computer (1, 4-8) caused by a fault or interrupt in the program run, program recovery points are provided which are time-dependent or can be preset in the main program of a useful program, and when these recovery points are reached, the computer status is stored in at least one fault-tolerant archival memory (5, 6). The computer status includes the status of the variables of a useful program being executed, the register status of the processor (1) and the register status of the input/output devices of the computer. During execution of the useful program, at least a part of the current computer status is stored in a main memory (4) and copied into an archival memory (6) when a program recovery point is reached.

Abstract: A new data storage device that includes one or more digital data storage elements, each element including a magnetic core, and an input addressing portion comprising a magnetic input addressing element for receiving at an input magnetic flux representing a data value and selectively coupling a flux to an output for transmission to a magnetic core in response to addressing flux generated therein. An output element magnetically coupled to a magnetic core detects transitions in magnetic flux in a magnetic core. In addition, the data storage element may further comprise an output addressing portion comprising a magnetic input addressing element for receiving at an input magnetic flux representative of flux in a magnetic core and selectively coupling a flux to an output in response to addressing flux generated therein.

Abstract: The present invention relates to a Bloch-line memory element and a nonvolatile RAM memory using such a Bloch-line memory element. The Bloch-line memory element comprises a planar magnetic memory element having magnetic domains separated by a wall which contains a Bloch-line disposed within the individual memory element. Coincident write lines interact with the magnetic element for writing a Bloch-line to a predetermined area within the memory element. For sensing the presence or absence of a Bloch-line within the predetermined area, one write conductor and a sense line are used for determining the logic state of the particular memory element. A plurality of memory elements are disposed in an address matrix and can be selected for reading from or writing to the particular Bloch-line RAM memory element for determining or writing bits of words.

Abstract: An integrated circuit memory having a plurality of row lines; a plurality of select lines; a plurality of output lines; a plurality of memory cells; each pair of memory cells having common outputs coupled to a select one of the plurality of output lines and common address inputs coupled to a select one of the plurality of row lines, wherein ambiguity of which memory cell of the pair of memory cells to be selected, being coupled to a select one of the plurality of row lines and a select one of the plurality of output lines, is determined by two selected ones of the plurality of select lines coupled thereto. Also provided is a first decoder, responsive to an input address, for enabling a select one of the plurality of row lines, and a second decoder, responsive to the row lines and to the input address, for enabling a select one of the select lines which corresponds to pairs of memory cells with an enabled row line.