Abstract: A semiconductor memory device, including a plurality of programmable read only memory cells arranged at intersection points of a matrix formed by a plurality of word-lines and bit-lines crossing each other, independently having first column transfer gate transistors located between a programming circuit and the bit-lines to transfer a programming data signal from the programming circuit to a selected memory cell located on one of the bit-lines when the memory device is in a programming mode and second column transfer gate transistors located between a sense amplifier and the bit-lines to transfer a read out data signal from a selected memory cell located on one of the bit-lines to a sensing amplifier when the memory device is in a reading mode.

Abstract: A sense amplifier is provided for a bipolar random access memory that has memory cells arranged in a column and a pair of bit lines for said column of memory cells. A first bipolar transistor has its collector-emitter path coupled to one of the bit lines of a pair, and a base coupled through a diode means to the second bit line. A second bipolar transistor has its collector-emitter path coupled to the second bit line and its base coupled through a second diode to the first bit line. The collectors of both of the bipolar transistors are coupled to provide an output signal. Resistors are coupled to a pulse source and to both of the bases of the bipolar transistors. A current sink is coupled to both of the select bit lines. The diode means are connected so as to be forward biased when the base-emitter junction of the transistor to which the diode means is coupled is also forward biased.

Abstract: The present invention provides a memory addressing system that can accommodate multiple size DRAMS. DRAMS of various sizes can be mixed in a variety of ways. The present invention provides a hardware register associated with each pair of banks of DRAMS. This hardware register is programmable to indicate the type of DRAMS that have been inserted in the particular memory banks and to indicate the starting address of the particular set of memory banks. Using this technique, it is not necessary to insert the largest memory chips in the first memory bank. Memory chips of either size can be inserted in either set of memory banks and the information in the programmable register is used to control circuitry which appropriately modifies the accessing signals which are sent to the memory system.

Abstract: A semiconductor memory device provided with an on-chip test circuit is disclosed. The on-chip test circuit includes a test write circuit for writing the same write data to at least two memory cells, simultaneously in a test mode, a selection circuit for simultaneously reading stored data from the above at least two memory cells and a comparison circuit for comparing data read from the at least two memory cells whose comparison output shows whether at least one of the at least two memory cells is bad, or all of the at least two memory cells are good.

Abstract: In video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.

Abstract: A magnetic solid state device, such as a magnetoresistive memory cell, includes first and second layers of magnetoresistive material. The first and second layers are separated by a third layer which prevents exchange coupling between the magnetic dipoles of the first and second layers. The first, second and third layers are formed as a strip. A fourth layer of a resistive material, such as nitrogen doped tantalum, overlies the first layer. The fourth layer includes spaced, raised portions over which electrically conductive material, such as TiW, may be formed on top of the raised portions.

Abstract: A static semiconductor memory device comprises a plurality of memory cells each connected to complementary bit line pairs and to word lines, a row decoder for selecting any of the word lines, and a load and a transfer gate connected to the bit line pairs. When data "0" or "1" is written into all of the memory cells, the load is cut off from the bit lines by a current cutoff circuit, the bit lines are fixed to a predetermined potential by a current fixing circuit, and all of the word lines are driven by a word line driving circuit, so that all of the memory cells simultaneously enter a common state.

Abstract: A printer/copier which stores job image data in memory before reproduction has a "refresh period" after which data stored therein will degrade if the device is not refreshed. Upon completion of a "security" job, DRAM refresh and normal read or write operations are disabled for a time period sufficient to allow the data resident in the DRAM to degrade.

Abstract: A storage device capable of being configured either as a single-access memory or as two separate memories is described. The storage device is especially suited for use in a digital signal processor performing numeric algorithms such as fast fourier transforms, autocorrelation and digital filtering because certain of such algorithms require fast dual access to two correlated, but separate, parameters while other such algorithms require fast single access to identical parameters. The storage device is shown in an exemplary embodiment empolying a multiplexer to affect writing of data from either of two data busses to one of the memories. In a second embodiment the write port of the memory is connected to one bus and the read port is connected to both busses. In this embodiment a dual-port address register file and a pair of address generation units provide indirect addressing capability for the storage device. Method of operating separate memories in a single-access or a dual-access mode is also described.

Abstract: An output circuit of a static random access memory is designed to set the output voltage of the data output circuit to an intermediate voltage by detecting the transition of the address signal before the data in a memory cell is read out from the memory cell, and then, the output voltage of the data output circuit is changed from the intermediate voltage to an H level or from the intermediate voltage to an L level. In this way, since the output voltage changes from the intermediate voltage to an H level or an L level, the transition time of the output voltage is shortened, and therefore the speed of a data reading operation may be increased. At the same time, the momentary current through the data output circuit may be decreased.

Abstract: A dual-port memory which features a pipelined serial port is disclosed. The serial side of the dual-port memory contains a ripple counter which is broken between predetermined stages. The contents of the stages above the break are decoded to select a group of bits of the serial register for output, and the contents latched in a latch. In serial output, the contents of the stages below the break are decoded, so that responsive to the stages below the break reaching a certain value, the stages above the break are incremented and the incremented value decoded. Pass transistors between the register and the latch are turned off during such time as the incremented value is being decoded, so that the new value will not disturb the output. The latched output is selectively presented by a multiplexer which selects the latch bits responsive to the value of the stages below the break. Upon the value of the stages reaching its minimum value (i.e.

Abstract: An EPROM structure incorporating Vss isolation transistors having gates on wordlines shared by respective rows of conventional self-aligned EPROM cells, and having source and drain regions connected in series between EPROM cell source regions and the ground Vss terminal. An isolation transistor becomes conductive only when an EPROM cell sharing its wordline is selected. During programming, otherwise possible leakage current through unselected cells sharing the selected bitline is blocked by the Vss isolation transistor. Only one unselected adjacent cell, which shares a common source region with the selected cell, can leak. This leakage, if properly suppressed and compensated, has no disturbance on unselected or selected cells during array programming. The EPROM cell drain punchthrough voltage and channel length can thus be reduced to obtain an EPROM cell with a low threshold voltage, low drain programming voltage, short programming time, low cell junction and bitline capacitance, and high read current.

Abstract: An EPROM structure incorporating Vss isolation transistors having gates on wordlines shared by respective rows of conventional self-aligned EPROM cells, and having source and drain regions connected in series between EPROM cell source regions and the ground Vss terminal. An isolation transistor becomes conductive only when an EPROM cell sharing its wordline is selected. During programming, otherwise possible leakage current through unselected cells sharing the selected bitline is blocked by the Vss isolation transistor. Only one unselected adjacent cell, which shares a common source region with the selected cell, can leak. This leakage, if properly suppressed and compensated, has no disturbance on the unselected or selected cells during array programming.

Abstract: A random-access memory having a plurality of memory cells each cell including a magnetic storage element in which the magnetic storage element inlcudes a thin film of magnetic material disposed on a semiconductor substrate and having further disposed thereon transistors connected in a flip-flop type of configuration. In a preferred embodiment of the invention, the magnetic storage element comprises a thin magnetic film that has mutually orthogonal remanent magnetization states used for information storage. A pair of strip conductors used to provide connections to the flip-flop configuration of the transducers are magnetically coupled to the mutually orthogonal remanent magnetization states. By providing the thin film having a pair of mutually orthogonal remanent states used for information storage, a storage cell having a relatively high frequency response is provided.

Abstract: Electrically programmable non-volatile memories, more currently known as EPROM memories. The memory according to the invention, using floating grid transistors with injection by hot carriers has an architecture which is different from that of conventional memories. Instead of having each transistor connected between a bit line and a mass line to Vss, here each transistor is connected between two adjacent bit lines; for example, in the drawing annexed, the transistor T12 of which the grid is controlled by the word line LM1, has its source connected to the bit line LB1 and its drain connected to the bit line LB2 immediately adjacent to LB1. Advantages result from such an arrangement from the point of view of size, since insulating the drains of the two adjacent transistors by means of a thick oxide is no longer necessary.

Abstract: A Bloch line memory device comprises stripe magnetic domains in a magnetic film for holding magnetic bubble domains. A pair of Bloch lines is stored as an information carrier in a magnetic wall constructing the stripe magnetic domain. A longitudinal direction of the stripe magnetic domain is made parallel to either the crystalographic directions [112] and [112], [121] and [121], or [211] and [211] of the magnetic film so that the pair of Bloch lines can be smoothly moved in the magnetic wall of the stripe magnetic domain.

Abstract: A differential amplifier having input terminals connected to first and second nodes lying between the main nonvolatile memory cell section and the nonvolatile dummy cell circuit is used as a sense amplifier. The first and second nodes are pre-charged to a high potential level prior to the data readout operation. The memory cell section and the dummy cell circuit are set in the capacitively balanced condition, thereby making it possible to correctly read out data at a high speed.

Abstract: A static row driver for an array of memory cells which includes a plurality of NAND gates each having a pair of row line driver input signals, an inverter coupled to an output of each of the NAND gates, a switch coupled to an output of each of the inverter circuits and a switch control coupled to each of the switches for opening an associated switch and passing the signal from a corresponding inverter output to an associated row line.

Abstract: A microcomputer is disclosed having a LIFO memory employed as a stack, and a shift register employed as a stack pointer for controlling access to the stack. There is no need to decode the contents of a stack pointer. Thus, high speed of operation is possible.

Abstract: A package comprised of a plurality of truncated confocal, ellipsoidal layers of substantially equal length and having a common opening therethrough along a central axis for receiving a micromagnetic memory therein, typically a vertically stacked bubble memory.