Abstract: In a semiconductor memory device with normal word lines and spare word lines, a partial decoder receives and decodes a predetermined two of the bit signals of the original logic levels of an address signal, and two of the bit signals of the complementary logic levels, which correspond to the predetermined two bit signals, and outputs different signal combinations of the predetermined two bit signals and the two corresponding bit signals. A spare word line selecting circuit receives the different signals and selects one of the different signals in order to select a spare word line which corresponds to a normal word line to which a defective cell is connected. The partial decoder may be used for both the normal word line selection and the selection of spare word lines. With a device constructed in such a manner, bit signals of an address signal are not directly input to the spare word line selecting circuit, but rather signals of different bit signal combinations are input to it.

Abstract: A nonvolatile semiconductor memory device comprising a matrix array of memory cells, word lines for driving the rows of memory cells, bit lines for reading data from columns of memory cells, a plurality of first MOS transistors provided for these bit lines, respectively, a second MOS transistor having a source coupled to the bit lines by the first MOS transistors, a drain coupled to a VCC terminal, and a gate connected to receive a predetermined bias voltage, a row decoder for selecting one of the word lines in accordance with a row-address signal, and a column decoder for turning on one of the first MOS transistors in accordance with a column-address signal.

Abstract: An erasable programmable logic device which includes a programmable AND memory array and a macrocell processing the output of the AND array allows product term sharing/allocation by adjacent macrocells. Two groups of four product terms each are coupled to each macrocell, wherein the OR'ing of each group of four product terms is each coupled to a multiplexor. One group is also coupled to a previously adjacent macrocell and the second group is coupled to a subsequently adjacent macrocell. A third and fourth multiplexor accept four product terms from each of the adjacent macrocells and the output of the four multiplexors are coupled to an OR gate. When a multiplexor is activated, it couples each grouping of four product terms to the OR gate and the output of the OR gate is coupled to an I/O circuit which emulates combinatory and sequential logic circuits. By selecting appropriate multiplexors each eight product term macrocell is capable of processing 0, 4, 8, 12 or 16 product terms.

Abstract: A semiconductor non-volatile memory device includes: a memory cell array having a plurality of memory cells, each including a non-volatile memory cell portion; a high voltage generating circuit for generating a high voltage required for storing data; a plurality of high voltage wirings, each being allocated to each of a corresponding plurality of blocks divided into units of a predetermined number of cells in the memory cell array and being commonly connected to all of the cells in a corresponding block; and a plurality of high voltage feeding circuits, each feeding the high voltage from the high voltage generating circuit to the cells in the corresponding block, and when a leak occurs in any one of the cells in the corresponding block, stopping the feed of the high voltage.

Abstract: Memory cells in a matrix are provided by a thin film of amorphous semiconductor material overlayed by a thin film of resistive material. An array of parallel conductors on one side perpendicular to an array of parallel conductors on the other side enable the amorphous semiconductor material to be switched in addressed areas to be switched from a high resistance state to a low resistance state with a predetermined level of electrical energy applied through selected conductors, and thereafter to be read out with a lower level of electrical energy. Each cell may be fabricated in the channel of an MIS field-effect transistor with a separate common gate over each section to enable the memory matrix to be selectively blanked in sections during storing or reading out of data. This allows for time sharing of addressing circuitry for storing and reading out data in a synaptic network, which may be under control of a microprocessor.

Abstract: A highly-integrated semiconductor dynamic random-acess memory is disclosed wherein a reference voltage-generating circuit is connected by voltage-transmission lines to a row-address buffer and a column-address buffer. The reference voltage-generating circuit receives a power-supply voltage and generates first and second reference voltages which are different, by different values, from an ordinary reference potential level. These reference voltages are supplied to the address buffers through the voltage-transmission lines. The first and second reference voltages are adjusted to compensate for a potential deviation which occurs on the voltage-transmission lines. Therefore, even when either reference voltage fluctuates due to an increase in the coupling capacitance between the substrate of the dynamic random-access memory, on the one hand, and the voltage-transmission lines, on the other, both address buffers are prevented from malfunctioning.

Abstract: This invention relates to a semiconductor memory having a high speed operation and a high integration density. When a high integration semiconductor memory is applied to a large scale computer system, storage data must be erased at a high speed for data security. The present invention erases the storage data by a method which is different from the write method of conventional prior art. In the invention, the erasing operation is made by continuously selecting word lines while sense amplifiers are kept in this on-state. The present invention includes a control circuit for attaining such an operation, and can be used for a semiconductor memory implemented in a computer system accessed by a plurality of users.

Abstract: A semiconductor memory uses cells with a ferroelectric capacitor having one plate coupled to a bit line by a FET and another plate coupled to a plate line. A pulse on the plate line causes the bit line to change voltage based on the state of the cell. A dummy cell arrangement is disclosed using one capacitor per cell, and another embodiment uses two capacitors per cell with no dummy. The cells cooperate with a sense amplifier and timing signals so that they are self restoring.

Abstract: A dynamic type semiconductor memory device with an improved bit line arrangement is disclosed. The memory device comprises at least first and second pairs of bit lines and a sense amplifier having a pair of input terminals to which one pair of bit lines among the first and second bit line pairs are selectively connected, and is featured in that the bit lines of the first bit line pair and the bit lines of the second bit line pair are alternately arranged in parallel.

Abstract: A pseudo static RAM includes an array of dynamic memory cells and peripheral circuits such as precharge transistors, a row decoder and sense amplifiers. Address change detecting circuits detect address signal change. A pulse generator supplies a pulse signal to a timing generator and a busy signal generator in response to the address signal change. The timing generator generates various timing signals for driving the peripheral circuits. When a subsequent address signal change is detected during operation of a dynamic RAM, a flag circuit generates a flag signal in response to a subsequent pulse signal from the pulse generator and a busy signal from the busy signal generator. Thus, the signal commanding such subsequent operation of the pseudo static RAM is stored in the form of a flag signal until the first operation is completed. Upon completion of first operation of the dynamic RAM, subsequent operation is started on the basis of the flag signal.

Abstract: An electrically programmable read only memory including a plurality of memory cells each composed of a field effect transistor having a floating gate is disclosed. The memory is featured by a test circuit which has a first circuit responding to a first control signal to raise all word lines up to a programming voltage and a second circuit responding to a second control signal to raise all digit lines up to the programming voltage. It is thereby detected whether or not electrons injected into the floating gate of the programmed memory cell are carried away during a data programming operation period.

Abstract: A memory arrangement is comprised of a plurality of memory chips, and address and control lines connected to the chips. In order to minimize the effect of interference of signals from the address lines on the control lines, the address lines coupled to a portion of the chips carry address signals in inverted form, as compared with the address signals applied to the remainder of the chips, whereby interference signals of opposite polarity are induced in the control lines and cancel each other.

Abstract: A nonvolatile semiconductor memory device comprises a cell transistor formed of a floating gate type MOS transistor, for storing an electric charge, whose gate is connected to a control gate line layer, a first selecting transistor formed of an MOS transistor, whose gate is connected to a read gate line layer, whose source-drain path is connected at one end to a read line layer, and at the other end to one terminal of the source-drain path of the cell transistor, and a second selecting transistor formed of an MOS transistor, whose gate is connected to a write gate line layer, whose source-drain path is connected at one end to a write line layer, and at the other end to the other terminal of the source-drain path of a cell transistor. A power source voltage of 5 V can be supplied to the read line layer in the read mode.

Abstract: A semiconductor memory device provided with an improved word line drive circuit is disclosed. The memory device comprises a pair of decoding units, a plurality of word lines, a plurality of N-channel transistors coupled between first ends of the word lines and the output terminal of one of the pair of decoding unit, and a plurality of P-channel transistors coupled between second, opposite ends of the word lines and the output terminal of the other of the pair of decoding units.

Abstract: A magnetic bubble memory device comprising a chip assembly having a plurality of bubble memory chips superposed one above the other on a main printed wiring film. The lowermost chip is electrically connected to wiring patterns formed on the main printed wiring film. Each of the upper chip or chips is mounted on an auxiliary printed wiring film and electrically connected to the wiring patterns of the main printed wiring film through the auxiliary printed wiring film. The chip assembly is assembled with coils for generating a revolutional magnetic field disposed in a magnetic shield case in such a manner that the bubble memory chips are disposed inside of the coils and both ends of the main printed wiring film are disposed outside of the coils for outer connection.

Abstract: A dual-port memory which features a pipelined serial port is disclosed. The serial side of the dual-port memory contains a ripple counter which is broken between predetermined stages. The contents of the stages above the break are decoded to select a group of bits of the serial register for output, and the contents latched in a latch. In serial output, the contents of the stages below the break are decoded, so that responsive to the stages below the break reaching a certain value, the stages above the break are incremented and the incremented value decoded. Pass transistors between the register and the latch are turned off during such time as the incremented value is being decoded, so that the new value will not disturb the output. The latched output is selectively presented by a multiplexer which selects the latch bits responsive to the value of the stages below the break. Upon the value of the stages reaching its minimum value (i.e.

Abstract: This invention relates generally to Static Random Access Memory (SRAM) cells and more particularly, relates to a SRAM cell wherein soft-error due to .alpha.-particle radiation is reduced by permitting the potential at the common-emitter node of the cross-coupled transistors of the memory cell to swing freely. Still more particularly, it relates to a SRAM cell wherein the common-emitter node of the cell is decoupled from a heavily capacitively loaded word line with its common constant current source by means of a constant current source or current mirror disposed in each cell between the common-emitter node and the word line.

Abstract: A BiCMOS static random access memory (SRAM) is disclosed, which has first and second stage sense amplifiers. Each column in the memory array is associated with a first stage sense amplifier, and the first stage sense amplifiers are arranged in groups, with each group connected in wired-AND fashion to a pair of local data lines. The column address is used to select one of the first stage sense amplifiers for sensing the state of the memory cell in the selected column. One second stage sense amplifier is associated with each group of first stage sense amplifiers, and the second stage sense amplifier associated with the group containing the selected first stage sense amplifier is selected, according to the most significant bits of the column address. The second stage sense amplifiers are connected to a data-out bus in wired-OR fashion, with the output of the selected second stage sense amplifier driving the data-out bus.

Abstract: A semiconductor memory device has a redundancy circuit for compensating a defective bit when it occurs in the main memory cells. The redundancy circuit includes spare memory cells, a spare row decoder for selecting the spare memory cells, a first circuit section for inhibiting the use of the main row decoder when the spare row decoder is used, and a second circuit section for selecting the spare row decoder when an address specifying the main row line connected to the defective memory cell is denoted.

Abstract: A semiconductor memory includes a memory cell (42) which utilizes a cross-coupled bipolar SCR latch. The latch includes two sense nodes (78) and (80). Sense node (78) has associated therewith an NPN transistor (82) and a PNP load transistor (84). Similarly, sense node (80) has associated therewith an NPN transistor (90) and a PNP load transistor (92) configured as an SCR. Each of these sense nodes is cross-coupled to the base of the NPN transistor connected to the opposite sense node. A forward biased PN junction is connected between an external Write circuit and the collector of each of the NPN transistors to provide an independent current path when changing from a low logic state to a high logic state. This decreases the recovery time when going from a saturated to a cut-off state for the NPN transistor.

Abstract: A BiCMOS static random access memory (SRAM) is disclosed, which has first and second stage sense amplifiers. Each column in the memory array is associated with a first stage sense amplifier, and the first stage sense amplifiers are arranged in groups, with each group connected in wired-OR fashion to a pair of local data lines. The column address is used to select one of the first stage sense amplifiers for sensing the state of the memory cell in the selected column. One second stage sense amplifier is associated with each group of first stage sense amplifiers, and the second stage sense amplifier associated with the group containing the selected first stage sense amplifier is selected, according to the most significant bits of the column address. The second stage sense amplifiers are connected to a data-out bus in wired-OR fashion, with the output of the selected second stage sense amplifier driving the data-out bus.