Abstract: Embodiments of the disclosure are directed to a system having a memory module, a voltage generation module, and a plurality of multiplexors. The memory module has a plurality of memory blocks. The voltage generation module supplies two or more voltage rails. The multiplexors are electrically connected to the voltage generation module. Each memory block is electrically connected to one of the multiplexors. Each multiplexor is configured to switch between the two or more voltage rails based on an operational parameter of each memory block. The operational parameter of each memory block may be process control speed, storage status, an operating mode, temperature, or any combination thereof. The operating mode may further be an active mode, a standby mode, and a deep sleep mode.

Abstract: A capacitive logic cell with complementary control, including a variable-capacitance electromechanical device having a fixed part and a mobile part, the electromechanical device comprising first, second, third and fourth electrodes mounted on the fixed part, and a fifth electrode mounted on the mobile part, the first electrode being connected to a terminal for supplying a first input logic signal, the second electrode being connected to a terminal for supplying a second input logic signal, complementary to the first input logic signal, the third electrode being connected to a terminal for supplying a first output logic signal, and the fourth electrode being connected to a terminal for supplying a second output logic signal, complementary to the first output logic signal.

Abstract: Programming field programmable gate array (FPGA) digital electronic integrated circuits (ICs) or other ICs that support partial reconfiguration, a particular FPGA having reconfigurable partitions and primitive variations configurable in each of the reconfigurable partitions, comprises: before writing configuration bitstreams to the FPGA, compiling and storing primitive bitstreams for different primitive functions that can be implemented on the particular FPGA; receiving input in a graphical user interface to connect graphical blocks representing functional logic of an algorithm to implement on the particular FPGA, the graphical blocks relating to reconfigurable logic; automatically determining a subset of the primitive functions comprising particular primitive functions that correspond to the graphical blocks; obtaining, from the digital storage, a subset of the primitive bitstreams that corresponds to the subset of the primitive functions; using partial reconfiguration operations, writing the subset of the p

Abstract: Noise is reduced in a circuit that converts voltage. A voltage conversion circuit includes a conversion transistor, a current source transistor, and a control circuit. In this voltage conversion circuit, the conversion transistor converts a potential of an input signal, the potential being changed from one of two different potentials to the other, by using predetermined current, and outputs the converted signal as an output signal. Furthermore, the current source transistor supplies the predetermined current. Then, in a case where the potential of the input signal is changed to the other potential, the control circuit stops supplying the predetermined current.

Abstract: A lighting fixture that provides an illumination light includes a wireless signal repeater configured to receive an input wireless signal and to transmit an output wireless signal that corresponds to the input wireless signal. The lighting fixture further includes an occupancy sensor configured to monitor a space and to output occupancy detection information indicating whether the space is occupied. The wireless signal repeater is configured to operate based on the occupancy detection information.

Abstract: Disclosed herein is a memory-type camouflaged logic gate using transistors having different threshold voltages. The camouflaged logic gate may include two or more candidate logic gates, memory, the output signal of which is adjusted based on two or more transistors having different threshold voltages, and a multiplexer for selectively outputting the output of one of the two or more candidate logic gates depending on the output signal of the memory.

Abstract: Methods and systems are directed to creating a physical unclonable function (PUF) on a Field Programmable Gate Array (FPGA) and generating a unique signature for a device. The method includes, in part, designing a PUF by taking advantages of programmable logic elements on the FPGA, and extracting uninitialized values associated with one or more storage elements comprised in the PUF when the FPGA is powered up. The extracted uninitialized values can be combined to generate the unique signature for the device. The one or more storage elements can be bi-stable memory cells that are mapped to look up tables (LUTs) on the FPGA. The coordinates of these LUTs can be determined based on hamming distance analysis. Alternatively, the one or more storage elements can be memory cells associated with boundary scan cells of a boundary scan chain.

Abstract: The present disclosure provides a data mutex filter circuit and a data mutex filtering method. The data mutex filter circuit has a main input terminal and a main output terminal and including a preprocessing sub-circuit and a 1st-stage filter sub-circuit to an Nth-stage filter sub-circuit which are cascaded, N being an integer greater than or equal to 2. The 1st-stage filter sub-circuit has an input terminal coupled to the preprocessing sub-circuit, and the Nth-stage filter sub-circuit has an output terminal coupled to the main output terminal. Each stage of filter sub-circuit is configured to compare whether input data currently received at the main input terminal is the same as history data stored therein, and feed back a comparison result to the preprocessing sub-circuit; the preprocessing sub-circuit outputs corresponding data to the 1st-stage filter sub-circuit according to the comparison result fed back by each stage of filter sub-circuit.

Abstract: According to various embodiments, an integrated circuit is described comprising a plurality of subcircuits having different signal transfer reaction times, a control circuit configured to form two competing paths from the plurality of subcircuits in response to a control signal, an input circuit configured to supply an input signal to the two competing paths and an output circuit configured to generate an output value depending on which of the competing paths has transferred the input signal with shorter reaction time.

Abstract: An elongated lighting module having an asymmetric illumination source formed from at least two rows of light emitting diodes (LEDs) that extend along the long axis of the module and are independently controllable. The lighting modules are powered via a wiring harness that extends down a support pole to a power converter stack having LED drivers to control the modules. The power supply for lighting module includes a power enclosure having individual light emitting drivers for powering the rows of light emitting diodes that can adjust the power level to compensate for the loss of power from another of the light emitting drivers. The power supply may also include a backup that can be switched over to power the rows of light emitting diodes in the event of a failure.

Abstract: A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

Abstract: A machine learning model for classifying different lighting loads based on properties of electrical current through the loads is built. The model is applied to electrical data gathered based on powering a target lighting load in order to classify the load. Based on load classification, operating parameter(s) to control operation of a dimmer to control power to the load are selected and the dimmer is configured with the selected parameter(s) to achieve desired dimmer operation in dimming the load.

Abstract: Methods, systems, and apparatus for performing phase operations. In one aspect, a method for performing a same phase operation on a first and second qubit using a third qubit prepared in a phased plus state includes: performing a first NOT operation on the third qubit; computing a controlled adder operation on the first, second and third qubit, comprising encoding the result of the controlled adder operation in a fourth qubit; performing a square of the phase operation on the fourth qubit; uncomputing the controlled adder operation on the first, second and third qubit; performing a CNOT operation between the first qubit and the third qubit, wherein the first qubit acts as the control; performing a CNOT operation between the second qubit and the third qubit, wherein the second qubit acts as the control; and performing a second NOT operation on the third qubit.

Abstract: Push-pull integrated circuit output drivers may interfere with communication by other entities on a bus when an integrated circuit is powered down. When there is no power and/or when the bonding pad is externally driven above the internal supply voltage, the substrate/body/well of the p-channel field effect transistor (PFET) of the output driver is biased to prevent its drain diode from becoming forward biased thereby preventing interference with communication on the bus. Also, when there is no power, driver is powered down or pull up is disabled, the gate of the driver PFET is driven to a voltage that ensures the driver PFET remains off when the bonding pad is externally driven above the internal supply voltage.

Abstract: An integrated circuit, and method of forming the same. The integrated circuit includes standard logic cells and a combined logic cell over a semiconductor substrate. Each standard logic cell includes a standard height, a width that is an integer multiple of a unit width, first and second power rails, and at least one transistor and interconnections configured to implement a logic function that produces a single logic output. The combined logic cell includes the standard height, a width that is an integer multiple of the unit width, the first and second power rails, and at least two transistors and interconnections configured to implement a first logic function and a second logic function. The first and second logic functions produce first and second logic outputs, respectively. The interconnections are configured to direct the first logic output and the second logic output to destinations outside the combined logic cell.

Abstract: A circuit receives an input signal having a first level and a second level. A logic circuit includes a finite state machine circuit, an edge detector circuit, and a timer circuit. The finite state machine circuit is configured to set a mode of operation of the circuit. The edge detector circuit is configured to detect a transition between the first and second level. The timer circuit is configured to determine whether the first or second level is maintained over an interval, which starts from a transition detected by the edge detector circuit. The finite state machine circuit is configured to change the mode of operation based on the timer circuit determining that the first or second level has been maintained over the interval.

Abstract: Methods, apparatus, systems, and articles of manufacture corresponding to a low area and high speed termination detection circuit with voltage clamping are disclosed. An example apparatus includes a transistor including a first control terminal, first current terminal and a second current terminal, the second current terminal adapted to be coupled to a load. The apparatus further includes a logic gate including an input coupled to the first current terminal. The apparatus further includes a current source including a second control terminal, a third current terminal coupled to a voltage rail and a fourth current terminal coupled to the first current terminal and the input of the logic gate.

Abstract: A lighting system for an electrical device includes one or more light sources coupled to an electrical outlet. The one or more light sources are configured to receive power from a power supply and configured to generate output light on at least one side edge of the electrical device. The lighting system includes a controller communicatively coupled to the one or more light sources. The controller is configured to receive a signal from an auxiliary unit and control the one or more light sources to operate between an on-state and an off-state responsive to the signal from the auxiliary unit.

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.

Abstract: An input/output module electrically coupled between a control circuit and an input/output pin is provided. The input/output module includes a pre-driver and a post-driver. The pre-driver is electrically coupled to the control circuit, and the post-driver is electrically coupled between the pre-driver and the input/output pin. The pre-driver generates a pull-up selection signal and a pull-down selection signal according to an input signal and an enable signal generated by the control circuit. The post-driver sets a voltage level of the input/output pin according to the pull-up and pull-down selection signals. When the enable signal is at a first logic level, the input/output pin has a high impedance. When the enable signal is at a second logic level, the voltage level of the input/output pin changes with a logic level of the input signal, wherein the first logic level and the second logic level are inverted.