Patents Examined by Jany Richardson
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Patent number: 11500412Abstract: A circuit system includes an interposer that has a first clock network and first and second integrated circuit dies that are mounted on the interposer. The first integrated circuit die includes a phase detector circuit, an adjustable delay circuit that generates a second clock signal in response to a first clock signal received from the first clock network, and a second clock network that generates a third clock signal in response to the second clock signal. The second integrated circuit die comprises a third clock network that generates a fourth clock signal in response to the first clock signal received from the first clock network. The phase detector circuit controls a delay provided by the adjustable delay circuit to the second clock signal based on a phase comparison between phases of the third and fourth clock signals.Type: GrantFiled: March 28, 2019Date of Patent: November 15, 2022Assignee: Intel CorporationInventors: Jeffrey Chromczak, Chooi Pei Lim, Lai Guan Tang, Chee Hak Teh, MD Altaf Hossain, Dheeraj Subbareddy, Ankireddy Nalamalpu
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Patent number: 11494315Abstract: An arbiter for use with a plurality of request signals is presented. The arbiter includes a sequence identifier to identify an order between the plurality of request signals. The arbiter provides a plurality of output signals in which each output signal is associated with a request signal. When the request signals are provided in a sequential order the output signals are provided in the identified sequential order. When the request signals are provided substantially at the same time the output signals are provided in an arbitrary sequential order. A corresponding signal arbitration method and an electronic circuit comprising the arbiter are also presented.Type: GrantFiled: April 20, 2021Date of Patent: November 8, 2022Assignee: Dialog Semiconductor B.V.Inventor: Paulus Augustinus Joanna Janssens
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Patent number: 11496133Abstract: Embodiments may provide a radiation hardened low-power data acquisition system-on-chip (SOC) suitable for space flight. The various embodiments may provide the radiation hardened low-power data acquisition SOC having a radiation hardened semiconductor die, a radiation hardened multiplexer integrated on the radiation hardened semiconductor die and configured to receive a plurality of analog signals and selectively output an analog signal of the plurality of analog signals, at least one radiation hardened analog to digital converted integrated on the radiation hardened semiconductor die and configured to convert the analog signal to a digital signal, and a radiation hardened serial communication interface integrated on the radiation hardened semiconductor die and configured to output the digital signal.Type: GrantFiled: July 29, 2021Date of Patent: November 8, 2022Assignee: United States of America as represented by the Administrator of NASAInventors: George Suarez, Jeffrey J. DuMonthier, Gerard T. Quilligan
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Patent number: 11489527Abstract: A three dimensional circuit system includes first and second integrated circuit (IC) dies. The first IC die includes programmable logic circuits arranged in sectors and first programmable interconnection circuits having first router circuits. The second IC die includes non-programmable circuits arranged in regions and second programmable interconnection circuits having second router circuits. Each of the regions in the second IC die is vertically aligned with at least one of the sectors in the first IC die. Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection. The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits. The circuit system may include additional IC dies. The first and second IC dies and any additional IC dies are coupled in a vertically stacked configuration.Type: GrantFiled: June 22, 2021Date of Patent: November 1, 2022Assignee: Intel CorporationInventors: Scott Weber, Aravind Dasu, Ravi Gutala, Mahesh Iyer, Eriko Nurvitadhi, Archanna Srinivasan, Sean Atsatt, James Ball
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Patent number: 11490474Abstract: A light fixture usable in train tunnels provides normal mode downlighting for track and walkway lighting and a selective task lighting mode where higher-lumen lighting is provided in at least the same downlighting direction as the track and walkway lighting. The normal lighting illumination level is at least 0.25 to 2.00 foot-candles at the illuminated surfaces. The task lighting mode provides at least 5.00 foot-candles to the same illuminated surfaces. The task lighting mode is achieved with the same light source that provides the normal mode lighting or with additional light sources that are activated together with or instead of the normal lighting mode light sources. The light sources can be a plurality light emitting diode (LED) engines that include a plurality of LEDs. The task lighting mode can also use another light source to provide additional task lighting up from the fixture.Type: GrantFiled: March 30, 2020Date of Patent: November 1, 2022Assignee: Autronic Plastics, Inc.Inventors: Daniel A. Lax, Agjah I. Libohova
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Patent number: 11487507Abstract: A bit cell circuit of a most-significant bit (MSB) of a multi-bit product generated in an array of bit cells in a compute-in-memory (CIM) array circuit is configured to receive a higher supply voltage than a supply voltage provided to a bit cell circuit of another bit cell corresponding to another bit of the multi-bit product. A bit cell circuit receiving a higher supply voltage increases a voltage difference between increments of an accumulated voltage, which can increase accuracy of an analog-to-digital converter determining a pop-count. A bit cell circuit of the MSB in the CIM array circuit receives the higher supply voltage to increase accuracy of the MSB which increases accuracy of the CIM array circuit output. A capacitance of a capacitor in the bit cell circuit of the MSB is smaller to avoid an increase in energy consumption due to the higher voltage.Type: GrantFiled: May 6, 2020Date of Patent: November 1, 2022Assignee: QUALCOMM IncorporatedInventors: Ye Lu, Zhongze Wang, Periannan Chidambaram
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Patent number: 11481192Abstract: A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit generates an output signal that transitions between the upper and lower supply voltages of the first voltage domain in response to transition of the first internal signal.Type: GrantFiled: June 30, 2021Date of Patent: October 25, 2022Assignee: Rambus Inc.Inventors: Frederick A. Ware, John Eric Linstadt
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Patent number: 11483003Abstract: A pseudo-complementary logic network according to this embodiment includes a first logic stage including a first pull-up circuit of an N-type transistor and a first pull-down circuit and a second logic stage including a second pull-up circuit and a second pull-down circuit of an N-type transistor, wherein an output signal of the second logic stage is provided as an input of the first pull-down circuit, and the first pull-up circuit includes the second pull-down circuit.Type: GrantFiled: December 9, 2019Date of Patent: October 25, 2022Assignee: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATIONInventors: Eun Hwan Kim, Jae-Joon Kim
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Patent number: 11470702Abstract: A system and method to determine a health status of a LED light string. The system (100) includes a circuit that includes a LED light string (110) and a pulsed current driver (115) of the LED light string. The circuit is connected to a power source (105). The system includes a current sensor (120) measuring a current through the circuit. The system includes a detecting device (130) determining a state of the circuit. The detecting device determines an expected current expected to be passing through the circuit where the expected current is associated with the state. The detecting device receives a current measurement from the current sensor during a time when the circuit is in the state. The detecting device determines a comparison between the current measurement and the expected current. The detecting device generates an output indicative of a health status of the circuit based on the comparison.Type: GrantFiled: January 23, 2018Date of Patent: October 11, 2022Assignee: SIGNIFY HOLDING B.V.Inventor: Paul Smola
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Patent number: 11469517Abstract: In some embodiments, a phased array antenna, includes a plurality of antenna modules arranged in an antenna lattice configuration to form the phased array antenna, wherein an antenna module of the plurality of antenna modules includes an antenna element packaged together with an amplifier.Type: GrantFiled: April 21, 2021Date of Patent: October 11, 2022Assignee: Space Exploration Technologies Corp.Inventors: Alireza Mahanfar, Souren Shamsinejad, Shaya Karimkashi Arani, Siamak Ebadi, Ersin Yetisir, Peter Sung Tri Hoang, Javier Rodriguez De Luis, Nil Apaydin
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Patent number: 11468293Abstract: A hybrid computing system comprising a quantum computer and a digital computer employs a digital computer to use machine learning methods for post-processing samples drawn from the quantum computer. Post-processing samples can include simulating samples drawn from the quantum computer. Machine learning methods such as generative adversarial networks (GANs) and conditional GANs are applied. Samples drawn from the quantum computer can be a target distribution. A generator of a GAN generates samples based on a noise prior distribution and a discriminator of a GAN measures the distance between the target distribution and a generative distribution. A generator parameter and a discriminator parameter are respectively minimized and maximized.Type: GrantFiled: December 13, 2019Date of Patent: October 11, 2022Assignee: D-WAVE SYSTEMS INC.Inventor: Fabian A. Chudak
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Patent number: 11460876Abstract: A method includes obtaining a plurality of entangled qubits, with high fault tolerance, represented by a lattice structure. The lattice structure includes a plurality of contiguous lattice cells. A first subset of the plurality of entangled qubits defines a first plane, and a second subset of the plurality of entangled qubits defines a second plane that is parallel to and offset from the first plane. The plurality of entangled qubits includes a defect qubit that is entangled with at least one face qubit on the first plane and at least one edge qubit on the second plane.Type: GrantFiled: July 11, 2019Date of Patent: October 4, 2022Assignee: PSIQUANTUM, CORP.Inventors: Naomi Nickerson, Hector Bombin Palomo, Benjamin Brown
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Patent number: 11451232Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.Type: GrantFiled: July 30, 2021Date of Patent: September 20, 2022Assignee: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Ramamoorthy Ramesh, Amrita Mathuriya
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Patent number: 11437998Abstract: An integrated circuit is disclosed, including a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits multiple data signals to the second latch circuit through multiple first conductive lines disposed on a front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit through multiple second conductive lines disposed on a backside, opposite of the front side, of the integrated circuit.Type: GrantFiled: February 26, 2021Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kam-Tou Sio, Jiun-Wei Lu
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Patent number: 11431341Abstract: A synchronization circuit includes a precharge circuit and a signal driving circuit. The precharge circuit precharges an output node to a first logic level. The signal driving circuit detects, in synchronization with a second dock signal having a phase leading a first clock signal, a logic level of an input signal and drives, in synchronization with the first clock signal, the output node to a second logic level according to the logic level of the input signal.Type: GrantFiled: April 9, 2021Date of Patent: August 30, 2022Assignee: SK hynix Inc.Inventor: Ji Hyo Kang
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Patent number: 11431340Abstract: This disclosure relates to a dual power supply detection circuit including first and second input stage field effect transistors, an inverter stage, a feedback stage field effect transistor, and first and second compensation circuits. The inverter stage includes a complimentary pair of transistors, and the complementary pair of transistors includes an NMOS transistor and a PMOS transistor configured and arranged so that gate lengths of the PMOS and NMOS transistors are different. The disclosure also relates to an integrated circuit including a dual power supply detection circuit.Type: GrantFiled: January 6, 2021Date of Patent: August 30, 2022Assignee: Nexperia B.V.Inventors: Geethanadh Asam, Robert Mossel, Walter Luis Tercariol
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Patent number: 11417704Abstract: A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits each have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When a potential corresponding to second data is input to each of the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring.Type: GrantFiled: October 7, 2019Date of Patent: August 16, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hajime Kimura, Yoshiyuki Kurokawa
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Patent number: 11410537Abstract: The subject disclosure relates to solutions for testing lighting systems and in particular, for verifying lighting system operability in the event of a power failure. A process of the disclosed technology can include steps for receiving an interrupt command, toggling an interrupt relay in response to the interrupt command, and measuring one or more lighting characteristics of the lighting array to determine if the second power supply can power the lighting array. Systems and machine-readable media are also provided.Type: GrantFiled: May 19, 2021Date of Patent: August 9, 2022Assignee: HEXMODAL TECHNOLOGIES LLCInventors: Christopher Hariz, Utkarsh Shah
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Patent number: 11411560Abstract: An electronic system, an integrated circuit die and an operation method thereof are provided. The integrated circuit die includes a plurality of interface circuit slices and a merging circuit. The transmission data stream sent from the transmitter die is split into a plurality of sub-data streams. Each of the interface circuit slices provides a physical layer to receive the corresponding one of the sub-data streams. The merging circuit is coupled to the interface circuit slices to receive the sub-data streams. The merging circuit merges the sub-data streams from the interface circuit slices back to the original data corresponding to the transmission data stream to be provided to an application layer. The merging circuit aligns the sub-data streams from the interface circuit slices in timing to mitigate different delays of the interface circuit slices.Type: GrantFiled: July 30, 2021Date of Patent: August 9, 2022Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei Yu, Yung-Sheng Fang, Chang-Ming Liu, Igor Elkanovich
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Patent number: 11387829Abstract: An integrated circuit and a signal transmission method thereof are provided. The integrated circuit includes a first power domain, a second power domain, and a weakly pull circuit. The first power domain is powered by a first power source, the second power domain is powered by a second power source, and the second power domain transmits a signal to the first power domain through a transmission path. The weakly pull circuit is signally connected to the transmission path. When the second power domain is in a power-off mode, the weakly pull circuit maintains the transmission path stably at a logic level to prevent unknown signals from entering the first power domain from the second power domain and disturbing the normal operation of the first power domain.Type: GrantFiled: December 22, 2020Date of Patent: July 12, 2022Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Lien-Hsiang Sung