Abstract: A light emitting device according to an embodiment of the present disclosure includes: a first layer including Alx2Inx1Ga(1-x1-x2) N (0<x1<1, 0?x2<1); a second layer that is provided on the first layer and includes Aly2Iny1Ga(1-y1-y2) N (0<y1<1, 0?y2<1) that is lattice relaxed with respect to the first layer; and a third layer that is provided on the second layer, includes Alz2Inz1Ga(1-z1-z2) N (0<z1<1, 0?z2<1) that is lattice relaxed with respect to the second layer, and includes an active layer. A lattice constant aGAN of GaN in an in-plane direction, a lattice constant al of the first layer in an in-plane direction, a lattice constant a2 of the second layer in an in-plane direction, and a lattice constant a3 of the third layer in an in-plane direction have a relationship of aGAN<a2<a1, a3.

Abstract: A semiconductor device includes a first conductive structure. The semiconductor device includes a first dielectric structure. The semiconductor device includes a second conductive structure. The first dielectric structure is positioned between a first surface of the first conductive structure and a surface of the second conductive structure. The semiconductor device includes an etch stop layer overlaying the first conductive structure. The semiconductor device includes a first spacer structure overlaying the first dielectric structure. The semiconductor device includes a second dielectric structure overlaying the first spacer structure and the etch stop layer.

Abstract: A display device comprises first and second pixels, a light-emitting layer, color conversion layers, and color filter layers, the light-emitting layer comprising first and second light-emitting elements in the first and second pixels, wherein the color conversion layers comprise first and second color conversion layers in the first and second pixels, the color filter layers comprise first and second color filter layers in the first and second pixels, the first and second light-emitting elements emit first light having a central wavelength range of a first wavelength, the first and second color conversion layers contain color conversion particles converting the first light into second light having a central wavelength range of a second wavelength longer than the first wavelength, the first color filter layer transmits the first light and blocks the second light, and the second color filter layer transmits the second light and blocks transmission of the first light.

Abstract: A semiconductor package includes a semiconductor die having opposing first and second main surfaces, a first power electrode on the first main surface and a second power electrode on the second main surface, a first lead having an inner surface attached to the first power electrode and a distal end having a first protruding side face extending substantially perpendicularly to the first main surface of the die, a second lead having an inner surface attached to the second power electrode and a distal end having a second protruding side face extending substantially perpendicularly to the second main surface of the die, and a mold compound enclosing at least part of the die and at least part of the first and second leads. The first lead includes a recess positioned in an edge of the inner surface. The second lead includes a recess positioned in an edge of the inner surface.

Abstract: A surface mountable light emitting diode (LED) package with inclined light emitting surface is presented herein. An optoelectronic component comprises the surface mountable package, which comprises a top surface, a cavity, and a mounting surface that is parallel to the top surface to facilitate an attachment, via an automatic surface mount technology pick-and-place equipment, of the mounting surface to a printed circuit board of the optoelectronic component. The cavity comprises a material that facilitates a transmission of electromagnetic radiation comprising visible light and infrared light, optoelectronic device(s) positioned within the cavity that generate and/or receive the electromagnetic radiation, and a light emitting surface that is adjacent to the top surface and that is inclined at an angle relative to a vertical axis of a plane of the top surface to facilitate, via the material, a transmission/reception of the electromagnetic radiation from/by the optoelectronic device(s).

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

Abstract: A structure is disclosed, comprising: a first field effect transistor, FET, comprising a first source terminal, a first drain terminal, a first layer or body of semiconductive material arranged to provide a first semiconductive channel connecting the first source terminal to the first drain terminal, and a gate terminal arranged with respect to the first semiconductive channel such that a conductivity of the first semiconductive channel may be controlled by application of a voltage to the gate terminal; and a second FET comprising a second source terminal, a second drain terminal, a second layer or body of semiconductive material arranged to provide a second semiconductive channel connecting the second source terminal to the second drain terminal, and the gate terminal, the second conductive channel being arranged with respect to the gate terminal such that a conductivity of the second channel may be controlled by application of a voltage to the gate terminal.

Abstract: A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.

Abstract: A method of forming a package is provided. The method comprises assembling on a carrier a stack of chip layers including a plurality of first chip layers and a second chip layer; encapsulating the stack of chip layers in a molding compound; removing the carrier to form a package main body; forming a redistribution layer on an exposed side of a first chip layer; and dividing the package main body to form a plurality of packages. Each first chip layer includes first chips and chip couplers. A chip package includes at least one chip stack and at least one chip coupler stack on a singulated redistribution layer. Each chip stack includes at least one chip from each chip layer, and each chip coupler stack includes at least one chip coupler and/or at least one chip coupler segment from each of the first chip layers.

Abstract: A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.

Abstract: A display substrate and a display device are provided. The display substrate includes a base and subpixels. The subpixel includes: a data line pattern; a power source signal line pattern including a portion extending in the first direction; and a subpixel driving circuitry. The subpixel driving circuitry includes two switching transistors, a driving transistor, and a storage capacitor. First and second electrode plates of the storage capacitor are coupled to a gate electrode of the driving transistor and the power source signal line pattern respectively. Second electrodes of the two switching transistors are coupled to a first electrode of the driving transistor. An orthogonal projection of the second electrode of at least one of the switching transistors onto the base at least partially overlaps an orthogonal projection of the power source signal line pattern onto the base, and at least partially overlaps an orthogonal projection of the second electrode plate of the storage capacitor onto the base.

Abstract: A sputtering target and a method for fabricating an electronic device using the same are provided. A sputtering target may include a carbon-doped GeSbTe alloy, wherein, for the carbon-doped GeSbTe alloy, an average grain diameter of a GeSbTe alloy after sintering is in a range of 0.5 ?m to 5 ?m, and a first ratio of an average grain diameter of carbon after the sintering is Y (?m) to the average grain diameter of the GeSbTe alloy after the sintering may be in a range of greater than 0.5 and equal to or less than 1.5. Alternatively, for the carbon-doped GeSbTe alloy, a condition of Y=X×(Z/100) may be satisfied, where an average grain diameter of a GeSbTe alloy after sintering is X (?m), an average grain diameter of carbon after the sintering is Y (?m), and a content of carbon is Z (at %).

Abstract: Various embodiments include combined lens and safety enclosure apparatuses and methods for forming the apparatuses. In one example a combined lens and safety enclosure apparatus for a light-emitting diode (LED) module is disclosed. The enclosure apparatus includes at least one plastic-material-based optical-lens element mounted over a plurality of LED elements, where a distance between the optical-lens element and any portion of any one of the plurality of LED elements is spaced away from each other by at least 0.8 mm. A driver-on-board (DoB) subsystem, including an electronic circuit configured to provide power to the plurality of LED elements, has a plastic-material-based optical enclosure mounted over the DoB subsystem. A distance between the optical enclosure and any portion of any of the electronic circuit is spaced away from optical enclosure by at least 0.8 mm. Other devices and methods are described.

Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.

Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.

Abstract: A method includes coating a release film over a carrier. The carrier includes a first material having a first Coefficient of Thermal Expansion (CTE), and a second material having a second CTE different from the first CTE. The method further includes placing a device die over the release film, encapsulating the device die in an encapsulant, and planarizing the encapsulant until the device die is revealed.

Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.

Abstract: A device and method for fabrication thereof is provided which results in corrosion resistance of metal flanges (802) of a semiconductor package, such as a quad flat no-lead package (QFN). Using metal electroplating (such as electroplating of nickel (Ni) or nickel alloys on copper flanges of the QFN package), corrosion resistance for the flanges is provided using a process that allows an electric current to reach the entire backside of a substrate (102) to permit electroplating. In addition, the method may be used to directly connect a semiconductor die (202) to the metal substrate (102) of the package.

Abstract: A method of forming a semiconductor device includes attaching a first local interconnect component to a first substrate with a first adhesive, forming a first redistribution structure over a first side of the first local interconnect component, and removing the first local interconnect component and the first redistribution structure from the first substrate and attaching the first redistribution structure to a second substrate. The method further includes removing the first adhesive from the first local interconnect component and forming an interconnect structure over a second side of the first local interconnect component and the first encapsulant, the second side being opposite the first side. A first conductive feature of the interconnect structure is physically and electrically coupled to a second conductive feature of the first local interconnect component.

Abstract: A display apparatus includes a substrate including a main display area and a component area. The component area includes an auxiliary display area and a transmission area. Main display elements are disposed in the main display area. Auxiliary display elements are disposed in the component area. A thin-film encapsulation layer covers the main display elements and the auxiliary display elements. An optical functional layer is disposed on the thin-film encapsulation layer and includes a polarization layer. The polarization layer includes a first portion disposed in the transmission area and a second portion disposed in the main display area and the auxiliary display area.