Abstract: A semiconductor transistor structure with reduced contact resistance includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer, and a recess in a contact region. The recess penetrates through the barrier layer and extends into the channel layer. An Ohmic contact metal is disposed in the recess. The Ohmic contact metal is in direct contact with a vertical side surface of the barrier layer in the recess and in direct contact with an inclined side surface of the 2DEG layer and the channel layer in the recess.

Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.

Abstract: A method of fabricating a display device, the method comprising: preparing a mother substrate having a first cell region and a second cell region, and a first target region and a second target region in the first cell region and the second cell region, respectively; providing an encapsulation material on a first printing region in the first target region to form a first encapsulation layer; and providing the encapsulation material on a second printing region in the second target region to form a second encapsulation layer, wherein a center of the second printing region is shifted from a center of the second target region in a specific direction.

Abstract: An encapsulant compound apparatus, includes a mechanical operator, and an insert disposed on a surface of the mechanical operator. The insert operates to capture foreign material in the encapsulant compound.

Abstract: Methods for making laser-marked packaged surface acoustic wave devices are provided. The method may include directly marking a surface of a piezoelectric substrate, where the opposite surface of the piezoelectric substrate includes a package structure encapsulating a surface acoustic wave device. The method may include exposing the surface of the piezoelectric substrate to light from a deep ultraviolet laser. By using a wavelength readily absorbed by the piezoelectric substrate, a relatively shallow marking may be made in the piezoelectric substrate. The markings may extend less than 1 micrometer into the piezoelectric substrate, and do not affect the structural integrity of the piezoelectric substrate or the operation of the packaged surface acoustic wave device.

Abstract: A chip package includes a semiconductor substrate, a first light-transmissive sheet, a second light-transmissive sheet, a first antenna layer, and a redistribution layer. The first light-transmissive sheet is disposed over the semiconductor substrate, and has a top surface facing away from semiconductor substrate and an inclined sidewall adjacent to the top surface. The second light-transmissive sheet is disposed over the first light-transmissive sheet. The first antenna layer is disposed between the first light-transmissive sheet and the second light-transmissive sheet. The redistribution layer is disposed on the inclined sidewall of the first light-transmissive sheet, and is in contact with an end of the first antenna layer.

Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a conductive cavity antenna over the first conductive layer and substrate. The conductive cavity antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the conductive cavity antenna, first conductive layer, and substrate. The conductive cavity extends vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects.

Abstract: An interconnect structure for a redistribution layer includes an intermediate via land pad; a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad; and an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad. The array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad. The array of lower conductive vias arranged within the horseshoe-shaped via array region does not overlap with the cluster of upper conductive vias.

Abstract: A method of fabricating self-aligned grids in a BSI image sensor is provided. The method includes depositing a first dielectric layer over a back surface of a substrate that has a plurality of photodiodes formed therein, forming a grid of trenches, and filling in the trenches with dielectric material to create a trench isolation grid. Here, a trench passes through the first dielectric layer and extends into the substrate. The method further includes etching back dielectric material in the trenches to a level that is below an upper surface of the first dielectric layer to form recesses overlaying the trench isolation grid, and filling in the recesses with metallic material to create a metallic grid that is aligned with the trench isolation grid.

Abstract: A mid-infrared light emitting diode is provided, including a graphene lower electrode layer, a black phosphorous layer, and a graphene upper electrode layer sequentially arranged along a thickness direction of the mid-infrared light emitting diode, in which the black phosphorous layer contacts the graphene lower electrode layer and the graphene upper electrode layer. A manufacturing method of the mid-infrared light emitting diode, a silicon photonic circuit and a manufacturing method thereof are also provided.

Abstract: Disclosed is a chip component including a substrate having a first surface and a second surface on an opposite side from the first surface, and a third surface connecting the first surface and the second surface to each other, an external surface resin configured to cover at least the third surface of the substrate, and a terminal electrode formed on the first surface of the substrate and exposed from the external surface resin. A recessed portion is formed in an end portion of the third surface of the substrate, the end portion being on the first surface side. The external surface resin is embedded in the recessed portion.

Abstract: A carrier film for performing a semiconductor package process on a mother substrate including a multi-layer circuit, a mother substrate, and a method of manufacturing a semiconductor package, the carrier film including a base material layer having a predetermined stiffness; and an adhesive layer configured to attach the base material layer onto the mother substrate, the adhesive layer including a water soluble material, wherein the carrier film includes a plurality of openings passing therethrough from a top surface to a bottom surface thereof.

Abstract: A chip packaging structure includes a chip, a redistribution layer, a solder ball, an encapsulant, and a stress buffer layer. The chip has an active surface and a back surface opposite to each other, and a peripheral surface connected to the active surface and the back surface. The redistribution layer is disposed on the active surface of the chip. The solder ball is disposed on the redistribution layer, and the chip is electrically connected to the solder ball through the redistribution layer. The encapsulant encapsulates the active surface and the back surface of the chip, the redistribution layer, and part of the solder ball. The stress buffer layer at least covers the peripheral surface of the chip. An outer surface of the stress buffer layer is aligned with a side surface of the encapsulant.

Abstract: The present disclosure relates to the field of display technology, and provides a display substrate and a method for manufacturing the same. The display substrate includes: a light-emitting substrate comprising a plurality of light-emitting regions which are arranged in parallel with a light propagation direction, and each light-emitting region is provided with a light-emitting layer; a defining layer provided on the light-emitting substrate and including a plurality of hollow-out portions, and the hollow-out portions correspond to the light-emitting regions one to one; and a plurality of micro-lenses provided in the hollow-out portions in a one-to-one correspondence manner. With the present disclosure, it is possible to prevent damage to an underlying light-emitting substrate when forming the micro-lenses and to enhance the stability of the micro-lenses.

Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a protective layer, and a plurality of contact plugs. The stack structures are disposed over the substrate. The protective layer conformally covers top surfaces and sidewalls of the stack structures. The contact plugs are respectively disposed over the substrate between the stack structures. One of the contact plugs includes a narrower portion and a wider portion over the narrower portion. In a top view, the wider portion is separated from an adjacent protective layer by a distance.

Abstract: An electronic assembly has a backside capping layer, a host wafer having a back surface bonded to a top surface of the backside capping layer except for cavities in the wafer formed over areas of the backside capping layer, the cavities having side surfaces of the wafer. Chiplets have backsides bonded directly to at least portion of the areas of the top surface of the backside capping layer. A lateral dielectric material between side surfaces of the chiplets and side surfaces of the wafer, mechano-chemically bonds the side surfaces of the chiplets to the side surfaces of the wafer.

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.

Abstract: An organic electroluminescence element includes an anode, an organic light emitting layer disposed on an upper side of the anode, a first functional layer disposed over the organic light emitting layer and including NaF, a second functional layer disposed over the first functional layer and including an organic material containing Yb, and a cathode disposed on an upper side of the second functional layer. A method of manufacturing an organic electroluminescence element, includes forming an anode, forming an organic light emitting layer on an upper side of the anode, forming a first functional layer including NaF over the organic light emitting layer, forming a second functional layer including an organic material containing Yb over the first functional layer, and forming a cathode on an upper side of the second functional layer.

Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.

Abstract: A method and related structure for a quad flat no-lead (QFN), dual flat no-lead (DFN) or small outline no-lead (SON) package without a leadframe. Disposing semiconductor chips face-up on a temporary carrier, disposing a first encapsulant layer around the semiconductor chip, the active layer and conductive stumps, forming a conductive layer and conductive contacts over the planar surface, disposing encapsulant over the first encapsulant layer, conductive layer and conductive contacts, forming a photoresist over the encapsulant with openings, forming conductive pads within the openings, forming a solderable metal system (SMS) or applying an organic solderability preservative (OSP) over the conductive pads, and cutting through the encapsulant around the chip to form the outline of a package.