Abstract: A method forms an HEMT transistor of the normally off type, including: a semiconductor heterostructure, which comprises at least one first layer and one second layer, the second layer being set on top of the first layer; a trench, which extends through the second layer and a portion of the first layer; a gate region of conductive material, which extends in the trench; and a dielectric region, which extends in the trench, coats the gate region, and contacts the semiconductor heterostructure. A part of the trench is delimited laterally by a lateral structure that forms at least one first step. The semiconductor heterostructure forms a first edge and a second edge of the first step, the first edge being formed by the first layer.

Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

Abstract: A multi-gate HEMT includes at least two gates, with at least one recessed the same depth or at a deeper depth in a barrier layer than at least one other gate. Recessing a gate decreases the thickness of the barrier layer beneath the gate, reducing a density of high mobility carriers in a two-dimensional electron gas layer (2DEG) conductive channel formed at the heterojunction of a barrier layer and a buffer layer below the recessed gate. The recessed gate can increase gate control of the 2DEG conductive channel. The multi-gate HEMT has at least one gate recessed the same depth or a deeper depth into the buffer layer than another gate, which forms at least two different turn-on voltages for different gates. This can achieve improvement of transconductance linearity and a positive shift of the threshold voltage.

Abstract: An image sensor includes a substrate having a first surface and a second surface that are opposite to each other. The substrate including a plurality of unit pixel regions having photoelectric conversion regions and floating diffusion regions disposed adjacent to the first surface. A pixel isolation pattern is disposed in the substrate and is configured to define the plurality of unit pixel regions. An interconnection layer is disposed on the first surface of the substrate. The interconnection layer includes a conductive structure having a connection portion that extends parallel to the first surface of the substrate and is spaced apart from the first surface of the substrate. Contacts extend vertically from the connection portion towards the first surface of the substrate. Each of the contacts are spaced apart from each other with the pixel isolation pattern interposed therebetween. The contacts are coupled to the floating diffusion regions, respectively.

Abstract: Disclosed is a semiconductor light emitting device including: A semiconductor light emitting device comprising: a semiconductor light emitting device chip including a plurality of semiconductor layers, and electrodes electrically connected to the plurality of semiconductor layers, the plurality of semiconductor layers including an active layer adapted to generate light by recombination of electrons and holes; an encapsulating member of a lens shape made of a light-transmitting thermoplastic resin having at least 90% transmissivity for light of a wavelength band ranging from 100 nm to 400 nm, for surrounding the semiconductor light emitting device chip; and an external substrate including conductive layers electrically connected to the electrodes of the semiconductor light emitting device chip. The encapsulating member is formed in a way that all faces of the encapsulating member are exposed to outside, except for a portion of the lower face thereof in contact with the external substrate.

Abstract: Some embodiments of the disclosure provide a semiconductor device. The semiconductor device includes: a doped substrate; a barrier layer, disposed on the doped substrate; a channel layer, disposed between the doped substrate and the barrier layer; and a doped semiconductor structure, disposed in the doped substrate, where a band gap of the barrier layer is greater than a band gap of the channel layer, and the doped substrate and the doped semiconductor structure have different polarities.

Abstract: A semiconductor chip includes: an epitaxial film made of gallium nitride; a semiconductor element disposed in the epitaxial film; a chip formation substrate including the epitaxial film and having a first surface, a second surface opposite to the first surface, and a side surface connecting the first surface and the second surface; and a convex and a concavity on the side surface.

Abstract: A monolithic component includes a field-effect power transistor and at least one first Schottky diode inside and on top of a gallium nitride substrate.

Abstract: A semiconductor device comprises a III-N device and a Field Effect Transistor (FET). The III-N device comprises a substrate on a first side of a III-N material structure, a first gate, a first source, and a first drain on a side of the III-N material structure opposite the substrate. The FET comprises a second semiconductor material structure, a second gate, a second source, and a second drain, and the second source being on an opposite side of the second semiconductor material structure from the second drain. The second drain of the FET is directly contacting and electrically connected to the first source of the III-N devices, and a via-hole is formed through a portion of the III-N material structure exposing a portion of the top surface of the substrate and the first gate is electrically connected to the substrate through the via-hole.

Abstract: In some embodiments, the present disclosure relates to a transistor device. The transistor device that includes a source contact disposed over a substrate. The source contact has a first side and an opposing second side disposed between a first end and an opposing second end. A drain contact is disposed over the substrate and is separated from the source contact along a first direction. A gate structure is disposed over the substrate between the source contact and the drain contact. The gate structure extends along the first side of the source contact facing the drain contact and also wraps around the first end and the opposing second end of the source contact.

Abstract: It is an object to provide a semiconductor device with less power consumption as a semiconductor device including a thin film transistor using an oxide semiconductor layer. It is an object to provide a semiconductor device with high reliability as a semiconductor device including a thin film transistor using an oxide semiconductor layer. In the semiconductor device, a gate electrode layer (a gate wiring layer) intersects with a wiring layer which is electrically connected to a source electrode layer or a drain electrode layer with an insulating layer which covers the oxide semiconductor layer of the thin film transistor and a gate insulating layer interposed therebetween. Accordingly, the parasitic capacitance formed by a stacked-layer structure of the gate electrode layer, the gate insulating layer, and the source or drain electrode layer can be reduced, so that low power consumption of the semiconductor device can be realized.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for transistors including first and second semiconductor materials between source and drain regions. An example apparatus includes a first semiconductor material and a second semiconductor material adjacent the first semiconductor material. The example apparatus further includes a source proximate the first semiconductor material and spaced apart from the second semiconductor material. The example apparatus also includes a drain proximate the second semiconductor material and spaced apart from the first semiconductor material. The example apparatus includes a gate located between the source and the drain.

Abstract: A group III nitride single crystal substrate including a main surface, the main surface including: a center; a periphery; an outer region whose distance from the center is greater than 30% of a first distance, the first distance being a distance from the center to the periphery; and an inner region whose distance from the center is no more than 30% of the first distance, wherein a ratio (?A??B)/?B is within the range of ±0.1%, wherein ?A is a minimum value of peak wave numbers of micro-Raman spectra in the inner region; and ?B is an average value of peak wave numbers of micro-Raman spectra in the outer region.

Abstract: Fabrication of an integrated circuit includes forming a photoresist layer over a substrate. Target regions defined on the substrate are exposed using a reticle that defines a first exposure window for a first doped structure of a first type; the first exposure window has a first plurality of openings and a first plurality of dopant blocking regions. A respective exposure dose for each of the target regions is determined by an exposure map and provides controlled variations in the size of the first plurality of openings across the plurality of target regions. Subsequent to the exposure and to developing the photoresist, a dopant is implanted into the substrate through the first plurality of openings.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.

Abstract: A transmit integrated circuit includes a light source configured to generate a beam of light. A receive integrated circuit includes a first photosensor. A transmit optic is mounted over the transmit and receive integrated circuits. The transmit optic is formed by a prismatic light guide and is configured to receive the beam of light. An annular body region of the transmit optic surrounds a central opening which is aligned with the first photosensor. The annular body region includes a first reflective surface defining the central opening and further includes a ring-shaped light output surface surrounding the central opening. Light is output from the ring-shaped light output surface in response to light which propagates within the prismatic light guide in response to the received beam of light and which reflects off the first reflective surface.

Abstract: A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

Abstract: A semiconductor device comprising stacked complimentary transistors are described. In some embodiments, the semiconductor device comprises a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET), and a second device over the first device. In an example, the second device comprises a depletion mode thin film transistor. In an example, a connector is to couple a first terminal of the first device to a first terminal of the second device.

Abstract: Embodiments of the invention include a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. A contact disposed on the p-type region includes a transparent conductive material in direct contact with the p-type region, a reflective metal layer, and a transparent insulating material disposed between the transparent conductive layer and the reflective metal layer. In a plurality of openings in the transparent insulating material, the transparent conductive material is in direct contact with the reflective metal layer.

Abstract: According to one embodiment, a nitride crystal includes first, second, and third nitride crystal regions. The third nitride crystal region includes Al, and is provided between the first and second nitride crystal regions. A third oxygen concentration in the third nitride crystal region is greater than a first oxygen concentration in the first nitride crystal region and greater than a second oxygen concentration in the second nitride crystal region. A third carbon concentration in the third nitride crystal region is greater than a first carbon concentration in the first nitride crystal region and greater than a second carbon concentration in the second nitride crystal region. A <0001> direction of the first nitride crystal region is one of a first orientation from the second nitride crystal region toward the first nitride crystal region or a second orientation from the first nitride crystal region toward the second nitride crystal region.