Abstract: The present disclosure relates to a thin-film transistor, a method for preparing the same, and a display substrate. The method for preparing the thin-film transistor includes the steps of forming a source electrode, a drain electrode, and an active layer, in which the step of forming the source electrode, the drain electrode, and the active layer includes: forming a first thin film from a first metal oxide material in an atmosphere of a first oxygen content; and forming a second thin film from a second metal oxide material in an atmosphere of a second oxygen content, in which the first thin film is configured to form the active layer, the second thin film is configured to form a source electrode and a drain electrode, and the second oxygen content is less than the first oxygen content.

Abstract: A method for porosifying a Ill-nitride material in a semiconductor structure is provided, the semiconductor structure comprising a sub-surface structure of a first Ill-nitride material, having a charge carrier density greater than 5×1017 cm?3, beneath a surface layer of a second Ill-nitride material, having a charge carrier density of between 1×1014 cm?3 and 1×1017 cm?3. The method comprises the steps of exposing the surface layer to an electrolyte, and applying a potential difference between the first Ill-nitride material and the electrolyte, so that the sub-surface structure is porosified by electrochemical etching, while the surface layer is not porosified. A semiconductor structure and uses thereof are further provided.

Abstract: A radiation-emitting semiconductor body having a semiconductor layer sequence includes an active region that generates radiation, an n-conducting region and a p-conducting region, wherein the active region is located between the n-conducting region and the p-conducting region, the p-conducting region includes a current expansion layer based on a phosphide compound semiconductor material, and the current expansion layer is doped with a first dopant incorporated at phosphorus lattice sites.

Abstract: The present disclosure describes epitaxial oxide high electron mobility transistors (HEMTs). In some embodiments, a HEMT comprises: a substrate; a template layer on the substrate; a first epitaxial semiconductor layer on the template layer; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer. The template layer can comprise crystalline metallic Al(111). The first epitaxial semiconductor layer can comprise (AlxGa1-x)yOz, wherein 0?x?1, 1?y?3, and 2?z?4, wherein the (AlxGa1-x)yOz comprises a Pna21 space group, and wherein the (AlxGa1-x)yOz comprises a first conductivity type formed via polarization. The second epitaxial semiconductor layer can comprise a second oxide material.

Abstract: A nitride semiconductor device includes a substrate; a first nitride semiconductor layer above the substrate; a block layer above the first nitride semiconductor layer; a first opening penetrating through the block layer; an electron transit layer and an electron supply layer provided sequentially above the block layer and along an inner surface of the first opening; a gate electrode provided above the electron supply layer to cover the first opening; a second opening penetrating through the electron supply layer and the electron transit layer; a source electrode provided in the second opening; and a drain electrode. When the first main surface is seen in a plan view, (i) the first opening and the source electrode each are elongated in a predetermined direction, and (ii) at least part of an outline of a first end of the first opening in a longitudinal direction follows an arc or an elliptical arc.

Abstract: A method that is part of a method of forming an elevationally-extending string of memory cells comprises forming an intervening structure that is elevationally between upper and lower stacks that respectively comprise alternating tiers comprising different composition materials. The intervening structure is formed to comprise an elevationally-extending-dopant-diffusion barrier and laterally-central material that is laterally inward of the dopant-diffusion barrier and has dopant therein. Some of the dopant is thermally diffused from the laterally-central material into upper-stack-channel material. The dopant-diffusion barrier during the thermally diffusing is used to cause more thermal diffusion of said dopant into the upper-stack-channel material than diffusion of said dopant, if any, into lower-stack-channel material. Other embodiments, including structure independent of method, are disclosed.

Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.

Abstract: A semiconductor thin film structure may include a substrate, a buffer layer on the substrate, and a semiconductor layer on the buffer layer, such that the buffer layer is between the semiconductor layer and the substrate. The buffer layer may include a plurality of unit layers. Each unit layer of the plurality of unit layers may include a first layer having first bandgap energy and a first thickness, a second layer having second bandgap energy and a second thickness, and a third layer having third bandgap energy and a third thickness. One layer having a lowest bandgap energy of the first, second, and third layers of the unit layer may be between another two layers of the first, second, and third layers of the unit layer.

Abstract: Method of making a current collecting grid for solar cells, including the steps of a) providing a continuous layer stack (1) on a substrate (8), the layer stack (1) including an upper (2) and a lower (3) conductive layer having a photoactive layer (4) interposed there between; b) selectively removing the upper conductive layer (2) and the photoactive layer (4) for obtaining a first contact hole (10) extending through the upper conductive layer (2) and photoactive layer (4) exposing the lower conductive layer (3); c) printing a front contact body (4) on the upper conductive layer (2) and a back contact body (5) in the first contact hole (10) on the lower conductive layer (3) and forming an electrically insulating first gap surrounding the back contact body (5) between the upper conductive layer (2) and the back contact body (2).

Abstract: A light-emitting device includes: a substrate; a plurality of light-emitting elements mounted to the substrate; and a phosphor layer provided on the plurality of light-emitting elements, the phosphor layer including: a plurality of phosphor particles, and a glass layer covering surfaces of the phosphor particles, wherein the phosphor particles are bonded to each other by the glass layer, and an air layer is formed between the phosphor particles.

Abstract: A Ga2O3-based semiconductor device includes a Ga2O3-based crystal layer including a donor, and an N-doped region formed in at least a part of the Ga2O3-based crystal layer.

Abstract: A High Electron Mobility Transistor structure having: a GaN buffer layer disposed on the substrate; a doped GaN layer disposed on, and in direct contact with, the buffer layer, such doped GaN layer being doped with more than one different dopants; an unintentionally doped (UID) GaN channel layer on, and in direct contact with, the doped GaN layer, such UID GaN channel layer having a 2DEG channel therein; a barrier layer on, and in direct contact with, the UID GaN channel layer. One of the dopants is beryllium and another one of the dopants is carbon.

Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.

Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer on a substrate, forming a carbon nanotube (CNT) layer on the first dielectric layer, forming a second dielectric layer on the carbon nanotube (CNT) layer, patterning a plurality of trenches in the second dielectric layer exposing corresponding portions of the carbon nanotube (CNT) layer, forming a plurality of contacts respectively in the plurality of trenches on the exposed portions of the carbon nanotube (CNT) layer, performing a thermal annealing process to create end-bonds between the plurality of the contacts and the carbon nanotube (CNT) layer, and depositing a passivation layer on the plurality of the contacts and the second dielectric layer.

Abstract: A display device includes a substrate; at least one data line disposed on the substrate; a first pattern disposed on the substrate and spaced apart from the data line; a first insulating layer at least partially disposed on the data line and the first pattern; an active layer disposed on the first insulating layer and at least partially overlapping with the first pattern; a first gate insulating layer disposed on the active layer; and a first electrode disposed on the first gate insulating layer and overlapping with the active layer, wherein the first electrode does not overlap with the data line in a direction parallel to an upper surface of the first insulating layer.

Abstract: An organic photoelectronic device includes a first electrode and a second electrode facing each other and a light-absorption layer between the first electrode and the second electrode and including a photoelectric conversion region including a p-type light-absorbing material and an n-type light-absorbing material and a doped region including an exciton quencher and at least one of the p-type light-absorbing material and the n-type light-absorbing material, wherein at least one of the p-type light-absorbing material and the n-type light-absorbing material selectively absorbs a part of visible light, and an image sensor includes the same.

Abstract: An electronic control device (2) for controlling a sensor (3) comprising a box-shaped body provided on one side with an electronic connector (21), suitable for coupling with an analogous electrical connector (31) associated with such a sensor (3). Such a device, inside such a box-shaped body, comprises electrical power supply means (22) for supplying said sensor, at least one electronic control board (23) for controlling said sensor, with which radio transmission means of the data detected by the sensors are associated.

Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

Abstract: Each of a plurality of light emitting elements has a hexagonal shape with a center. An interior angle at each of corners is less than 180°. The plurality of light emitting elements include a first light emitting element having a first lateral side surface and a second light emitting element having a second lateral side surface. An orientation of the hexagonal shape of the second light emitting element is rotated by 30 degrees plus 30°+60°×N (N is an integer) with respect to the center of the second light emitting element relative to an orientation of the hexagonal shape of the first light emitting element such that the second lateral side surface is not parallel to the first lateral side surface.

Abstract: Solid state sources offers potential advantages including high brightness, electricity savings, long lifetime, and higher color rendering capability, when compared to incandescent and fluorescent light sources. To date however, many of these advantages, however, have not been borne out in providing white LED lamps for general lighting applications. The inventors have established that surface recombination through non-radiative processes results in highly inefficient electrical injection. Exploiting in-situ grown shells in combination with dot-in-a-wire LED structures to overcome this limitation through the effective lateral confinement offered by the shell the inventors have demonstrated core-shell dot-in-a-wire LEDs, with significantly improved electrical injection efficiency and output power, providing phosphor-free InGaN/GaN nanowire white LEDs operating with milliwatt output power and color rendering indices of 95-98.