Abstract: The present invention discloses methods for manufacturing a capacitor of a semiconductor device employing doped silicon film as an electrode and an oxide film-nitride film-oxide film as a dielectric film. An interlayer insulating film is formed on a semiconductor substrate. A storage electrode is formed consisting of a doped polysilicon on the interlayer insulating film. A first oxide film is formed on the storage electrode that is subjected to a thermal treatment in an atmosphere containing an n-type impurity to implant the impurity into the first oxide film. A nitride film is formed on the first oxide film, whereby the impurity in the first oxide film is diffused into the nitride film. A second oxide film is formed on the nitride film. A plate electrode is then formed on the second oxide film.

Abstract: This invention pertains to a method for making a trench capacitor of DRAM devices. A single-sided spacer is situated on the sidewall of a recess at the top of the trench capacitor prior to the third polysilicon deposition and recess etching process. The single-sided spacer is formed on the second polysilicon layer and collar oxide layer. Then, the third polysilicon deposition and recess etching process is carried out to form a third polysilicon layer on the second polysilicon layer. Dopants of the third polysilicon layer are blocked from diffusing to the substrate by the single-sided spacer.

Abstract: The present invention provides a method for eliminating inverse narrow width effects in the fabrication of DRAM devices. A semiconductor substrate is provided having thereon a shallow trench. The shallow trench surrounds an active area. A non-doped silicate glass (NSG) layer is deposited to fill the shallow trench, and is then etched back to a depth of the shallow trench, thereby exposing a portion of the semiconductor substrate at an upper portion of the shallow trench. A doped dielectric layer is deposited over the remaining NSG layer to cover the exposed semiconductor substrate. A thermal process is then carried out to diffuse dopants of the doped dielectric layer into the semiconductor substrate, thereby forming a doped region at the periphery of the active area in a channel width direction.

Abstract: The invention includes capacitor constructions comprising a layer of aluminum oxide between a high-k dielectric material and a layer comprising titanium and nitrogen. The layer comprising titanium and nitrogen can be, for example, titanium nitride and/or boron-doped titanium nitride. The capacitor constructions can be incorporated into DRAM cells, which in turn can be incorporated into electronic systems. The invention also includes methods of forming capacitor constructions.

Abstract: A method of preventing the cathode of an active matrix organic light emitting diode from breaking. A substrate having an array of thin film transistors thereon is provided. Each thin film transistor includes a gate electrode, a channel layer, a source terminal and a drain terminal. A passivation layer is formed over the substrate and then the passivation layer is planarized. Thereafter, an opening that exposes the drain terminal is formed in the passivation layer. An anode layer is formed over the passivation layer and the interior of a portion of the opening so that the drain terminal and the anode layer are electrically connected. A light-emitting layer and a cathode layer are sequentially formed over the substrate to form an active matrix organic light emitting device.

Abstract: A method for producing a nitride semiconductor comprising growing at least first to third nitride semiconductor layers on a substrate; said first nitride semiconductor layer being grown at 400–600° C.; and said second and third nitride semiconductor layers being grown on said first nitride semiconductor layer at 700–1,300° C. after heat-treating said first nitride semiconductor layer at 700–1,300° C.; used as a carrier gas supplied near said substrate together with a starting material gas being a hydrogen/nitrogen mixture gas containing 63% or more by volume of hydrogen during growing said second nitride semiconductor layer, and a hydrogen/nitrogen mixture gas containing 50% or more by volume of nitrogen during growing said third nitride semiconductor layer; and said second nitride semiconductor layer being formed to a thickness of more than 1 ?m.

Abstract: A semiconductor device with a bitline structure has a stud type capping layer. A method of fabricating the same achieves sufficient process margins and reduces parasitic capacitance. The device may include an insulating film formed on a semiconductor substrate and having a bitline contact and a groove-shaped bitline pattern, a bitline formed on the bitline contact and on a portion of the bitline pattern and that is surrounded by the insulating film, and a bitline capping layer formed on the bitline within the bitline pattern and the insulating film that protrudes from the insulating film. A protruded portion of the bitline capping layer is wider than the width of the bitline.

Abstract: A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diode or diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown,” the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.

Abstract: A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.

Abstract: Disclosed is a method and apparatus that features deposition of tantalum films employing sequential deposition techniques, such as Atomic Layer Deposition (ALD). The method includes serially exposing a substrate to a flow of a nitrogen-containing gas, such as ammonia NH3, and a tantalum containing gas. The tantalum-containing gas is formed from a precursor, (tBuN)Ta(NEt2)3 (TBTDET), which is adsorbed onto the substrate. Prior to adsorption of TBTDET onto the substrate layer, the TBTDET precursor is heated within a predefined temperature range.

Abstract: A method for forming a buried plate in a trench capacitor is disclosed. The trench is completely filled with a dopant source material such as ASG. The dopant source material is then recessed and the collar material is deposited to form the collar in the upper portion of the trench. After drive-in of the dopants to form the buried plate, the dopant source material is removed and the collar materials may be removed.

Abstract: A method for forming a self-aligned buried strap in a vertical memory cell. A semiconductor substrate with a trench is provided. A collar dielectric layer is conformally formed on the trench bottom portion, and the trench is filled with a conducting layer. The collar dielectric layer is etched below the level of the surface of the conducting layer to form a groove between the conducting layer and the trench. The groove is filled with a doped conducting layer. The dopant in the doped conducting layer is diffused to the semiconductor substrate in an ion diffusion area as a buried strap. The conducting layer and the doped conducting layer are etched below the ion diffusion area. A top trench insulating layer is formed on the bottom of the trench, wherein the top trench insulating layer is lower than the ion diffusion area.

Abstract: A method for forming a low-k dielectric layer for a semiconductor device using an ALD process including (a) forming predetermined interconnection patterns on a semiconductor substrate, (b) supplying a first and a second reactive material to a chamber having the substrate therein, thereby adsorbing the first and second reactive materials on a surface of the substrate, (c) supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, (d) supplying a third reactive material to the chamber, thereby causing a reaction between the first and second materials and the third reactive material to form a monolayer, (e) supplying a second gas to the chamber to purge the third reactive material that remains unreacted in the chamber and a byproduct; and (f) repeating (b) through (e) a predetermined number of times to form a SiBN ternary layer having a predetermined thickness on the substrate.

Abstract: The present invention provides a method of fabricating a silicon fin useful in preparing FinFET type semiconductor structures. The method is particularly useful for creating fins with a width and smoothness appropriate for sub-50 nm type gates. The method begins with a silicon fin prepared by lithographic means from an SOI type structure such that the fin is larger in dimension, particularly width, than is desired in the final fin. If desired the silicon fin can include a nitride cap. A conformal diffusion layer, such as of silicon dioxide, is then deposited onto the fin and silicon dioxide substrate. A PECVD deposition using TEOS gas is one method to deposit the diffusion layer. The coated fin is then heated and exposed to oxygen. The oxygen diffuses through the diffusion layer and converts a portion of the silicon material to silicon dioxide. This oxidation continues until a desired amount of silicon material is converted to SiO2 such that the remaining silicon has the desired dimensions.

Abstract: A method for manufacturing a semiconductor device is disclosed. One example manufacturing method includes successively depositing gate insulating layer forming material and gate electrode forming material on a semiconductor substrate and patterning the gate insulating layer forming material and the gate electrode forming material to form a gate insulating layer and a gate electrode. The example manufacturing method further includes performing a nitrogen ion-implantation to a front face of the substrate and annealing the substrate so as to form a re-oxidation layer that has different thickness on the sidewalls of the gate electrode and on the substrate. The example method results in semiconductor gate electrodes and sidewalls having different oxidation rates so that a thickness of the re-oxidation layer of the sidewalls of the gate electrode is relatively thickened.

Abstract: A first DRAM section including a first memory cell having a first capacitance and a second DRAM section including a second memory cell having a second capacitance different from the first capacitance are provided on the same semiconductor substrate.

Abstract: Systems and methods are provided for an on-chip decoupling device and method. One aspect of the present subject matter is a capacitor. One embodiment of the capacitor includes a substrate, a high K dielectric layer doped with nano crystals disposed on the substrate, and a top plate layer disposed on the high K dielectric layer. According to one embodiment, the high K dielectric layer includes Al2O3. According to other embodiments, the nano crystals include gold nano crystals and silicon nano crystals. One capacitor embodiment includes a MIS (metal-insulator-silicon) capacitor fabricated on silicon substrate, and another capacitor embodiment includes a MIM (metal-insulator-metal) capacitor fabricated between the interconnect layers above silicon substrate. The structure of the capacitor is useful for reducing a resonance impedance and a resonance frequency for an integrated circuit chip. Other aspects are provided herein.

Abstract: In a method for forming patterned ceramic layers, a ceramic material is deposited on a substrate and is subsequently densified by heat treatment, for example. In this case, the initially amorphous material is converted into a crystalline or polycrystalline form. In order that the now crystalline material can be removed again from the substrate, imperfections are produced in the ceramic material, for example by ion implantation. As a result, the etching medium can more easily attack the ceramic material, so that the latter can be removed with a higher etching rate. Through inclined implantation, the method can be performed in a self-aligning manner and the ceramic material can be removed on one side, by way of example, in trenches or deep trench capacitors.

Abstract: Disclosed is a method of manufacturing a deep trench capacitor structure that forms a trench in a substrate, lines the trench with a polysilicon liner, and forms titanium nitride columns along the polysilicon liner. The method etches the titanium nitride columns using chlorine-based dry chemistry that is substantially isotropic. This etching process removes the upper portion of the titanium nitride columns without affecting the polysilicon liner. The etching process attacks only in the uppermost portion of the titanium nitride columns such that, after the etching process is completed, the remaining lower portions of the titanium nitride columns are substantially unaffected by the etching process. Then, the method fills the space between the titanium nitride columns and the upper portion of the trench with additional polysilicon material. The process of filling the space simultaneously forms a polysilicon plug and polysilicon cap.

Abstract: An apparatus and a method for manufacturing semiconductor devices is disclosed for selectively disconnecting a fuse element out of plural fuse elements formed on a semiconductor wafer substrate which is provided with the plural fuse elements and a dielectric layer having at least one opening corresponding to the location for the plural fuse elements.