Abstract: A method of forming a buried collar on the sidewall of a trench in a semiconductor substrate including: (a) providing the trench in the semiconductor substrate, the trench having a first dielectric layer formed on a sidewall in a upper region of the trench and a conductive material filling a lower region of the trench, the conductive material covering a lower portion of the first dielectric layer; (b) removing the first dielectric layer not covered by the conductive material; (c) forming a second dielectric layer on the exposed sidewall of the upper region and on a top surface of the conductive material; (d) removing an uppermost portion of the second dielectric layer from the sidewall in the upper region; (e) forming a third dielectric layer on the exposed sidewall of the upper region; and (f) increasing the thickness of the second dielectric layer to form the buried collar.

Abstract: A method for crystallizing an amorphous film by doping phosphorus and using FE-MIC, and method for fabrication an LCD by using the same. The method for crystallizing an amorphous film includes forming an amorphous film containing an impurity on a substrate, forming a metal layer on the amorphous film, heat treating the amorphous film, and applying an electric field to the amorphous film.

Abstract: Upon formation of semiconductor micro patterns, an interlayer alignment error occurs due to asymmetry of each alignment mark. Prior to alignment of a mask with a wafer, the asymmetry of each alignment mark is measured according to the principle of a scatterometry, and the alignment is performed in consideration of the result of measurement to execute exposure. Thus, high-accuracy alignment can be carried out without sacrificing throughput, and the performance of a semiconductor device is improved. Further, manufacturing yields can be enhanced and a reduction in cost can be realized.

Abstract: A trench capacitor, in particular for use in a semiconductor memory cell, has a trench formed in a substrate; an insulation collar formed in an upper region of the trench; an optional buried plate in the substrate region serving as a first capacitor plate; a dielectric layer lining the lower region of the trench and the insulation collar as a capacitor dielectric; a conductive second filling material filled into the trench as a second capacitor plate; and a buried contact underneath the surface of the substrate. The substrate has, underneath its surface in the region of the buried contact, a doped region introduced by implantation, plasma doping and/or vapor phase deposition. A tunnel layer, in particular an oxide, nitride or oxinitride layer, is preferably formed at the interface of the buried contact. A method for producing a trench capacitor is also provided.

Abstract: Methods of forming a uniform cell nitride dielectric layer over varying substrate materials such as an insulation material and a conductive or semiconductive material, methods of forming capacitors having a uniform nitride dielectric layer deposited onto varying substrate materials such as an insulation layer and overlying conductive or semiconductive electrode, and capacitors formed from such methods are provided. In one embodiment of forming a uniform cell nitride layer in a capacitor construction, a surface-modifying agent is implanted into exposed surfaces of an insulation layer of a capacitor container by low angle implantation to alter the surface properties of the insulation layer for enhanced nucleation of the depositing cell nitride material, preferably while rotating the substrate for adequate implantation of the modifying substance along the top corner portion of the container.

Abstract: A semiconductor device containing a dielectric capacitor having an excellent step coverage for a device structure of high aspect ratio corresponding to high integration degree, as well as a manufacturing method therefor are provided. A dielectric capacitor of high integration degree is manufactured by forming a bottom electrode 46 and a top-electrode 48 comprising a homogeneous thin Ru film with 100% step coverage while putting a dielectric 47 therebetween on substrates 44, 45 having a three-dimensional structure with an aspect ratio of 3 or more by a MOCVD process using a cyclopentadienyl complex within a temperature range from 180° C. or higher to 250° C. or lower.

Abstract: A semiconductor device comprises a field effect transistor and a passive capacitor, wherein the dielectric layer of the capacitor is comprised of a high-k material, whereas the gate insulation layer of the field effect transistor is formed of an ultra thin oxide layer or oxynitride layer so as to provide for superior carrier mobility at the interface between the gate insulation layer and the underlying channel region. Since carrier mobility in the capacitor is not of great importance, the high-k material allows the provision of high capacitance per unit area while featuring a thickness sufficient to effectively reduce leakage current.

Abstract: The present invention relates to a method for manufacturing a liquid crystal display utilizing the dispense-injection method, and it is an object of the invention to provide a method for manufacturing a liquid crystal display which allows an optimum quantity of liquid crystals to be dispensed on each substrate. At a dispense-injection step, in the case of a two-shot process for fabricating two liquid crystal display panels from a single glass substrate, the heights of support posts on two CF substrates having columnar spacers formed thereon are measured at a plurality of points (e.g., five locations) on each of the surfaces using a laser displacement gauge and an average value of the height is obtained. The support post height of the columnar spacers is thus measured in advance to control the quantity of dispensed liquid crystals based on the measured value.

Abstract: A method of fabricating an annealed wafer of high quality by forming a defect-free active region of a device and controlling an irregular resistivity characteristic. The method includes a first annealing step of pre-heating a silicon wafer at a temperature of about 500° C. in a furnace in an ambience of a gas selected from the group consisting of Ar, N2 and an inert gas including Ar and N2; a second annealing step of changing the ambience of the gas into a 100% H2 gas ambience, increasing the temperature to 850° C.-1,150° C., and carrying out annealing for about an hour by maintaining the increased temperature; a third annealing step of changing the ambience of the gas into a 100% Ar gas ambience, increasing the temperature to about 1,200° C., and carrying out annealing for about an hour while the temperature of about 1,200° C. is maintained; and a temperature dropping step of decreasing the temperature in the furnace below about 500° C.

Abstract: In SOI integrated circuits having trench capacitor DRAM arrays, the decreasing thickness of the insulating layer causes cross-talk between the passing wordline traveling over the trench capacitor. Increasing the depth of the recess at the top of the trench and undercutting the insulating layer laterally permits the buried strap from the capacitor center electrode to make contact to the back side of the SOI layer, thereby increasing the vertical separation between the passing wordline and the strap.

Abstract: The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern is performed.

Abstract: The present invention aims to provide a field effect transistor which inhibits an aggregation of silicon atoms attendant on heat treatment and has stable source/drain shapes. The field effect transistor according to the present invention is manufactured using a substrate on which a silicon layer, an buried oxide film (BOX film) and an SOI layer are stacked in order. The field effect transistor has an element isolation layer formed in the SOI layer and further includes visored portions provided so as to cover angular portions on the main surface side of an activation layer defined by the element isolation layer.

Abstract: Ferroelectric memory cells are produced according to the stack principle. An adhesive layer is formed between a capacitor electrode of a memory capacitor and a conductive plug. An oxygen diffusion barrier is formed above the adhesive layer and once the ferroelectric has been deposited, the adhesive layer and the barrier are subjected to rapid thermal processing (RTP) in an oxygen atmosphere. An oxygen rate of the adhesive layer and the diffusion coefficient of oxygen in the material of the adhesive layer dependent on the temperature are determined. A diffusion coefficient of silicon in the material of the adhesive layer, dependent on the temperature, is determined. A temperature range for the RTP step from the two diffusion coefficients, determined for a predetermined layer thickness and layer width of the adhesive layer and the oxygen diffusion barrier is calculated, therefore, the siliconization of the adhesive layer occurs more rapidly than its oxidation.

Abstract: According to one example method of fabricating a semiconductor memory device, an isolation layer and a capping layer are formed on a silicon substrate, sequentially. By an epitaxial silicon growth process, an epitaxial active region is formed. A gate insulation layer and a gate electrode are then formed on the epitaxial active region, sequentially. Subsequently, a bit line contact plug and a storage node contact plug are epitaxially formed on the epitaxial active region. A lower interlayer insulation layer is formed on the resultant structure and planarized. An upper interlayer insulation layer is formed on the lower interlayer insulation layer and a bit line is formed therein. An additional upper interlayer insulation layer is then formed on the entire surface of the resultant structure and a storage node electrode is formed through the additional upper and the upper interlayer insulation layer to be connected to the storage node contact.

Abstract: A method of monitoring heat dissipation behavior of a fuse element formed in an integrated circuit structure is provided. A fuse element is fabricated in an integrated circuit structure. A plurality of resistors are formed adjacent the fuse element, wherein a resistivity of the resistors is temperature dependent. The fuse element is triggered, whereby heat is dissipated into the integrated circuit structure. A resistance change in the resistors is monitored to determine the heat dissipation behavior of the fuse element during triggering.

Abstract: A process including: creating a composition composed of a liquid and a self-organizable polymer at least partially dissolved in the liquid, resulting in dissolved polymer molecules; reducing the solubility of the dissolved polymer molecules to induce formation of structurally ordered polymer aggregates in the composition; depositing a layer of the composition including the structurally ordered polymer aggregates; and drying at least partially the layer to result in a structurally ordered layer, wherein the structurally ordered layer is part of an electronic device and the structurally ordered layer exhibits increased charge transport capability.

Abstract: Generation of stain-like display defects is prevented. There are provided in a liquid crystal-side pixel region of one substrate of respective substrates that are disposed to oppose each other with liquid crystals interposed therebetween a thin-film transistor being driven by a scan signal from a gate signal line, a pixel electrode to which an image signal from a drain signal line is supplied from this thin-film transistor, a protective film that is formed to also cover the thin-film transistor and the pixel electrode, and a resin film as formed on an upper surface of this protective film.

Abstract: A process for the heat treatment of a silicon wafer, during which the silicon wafer is at least temporarily exposed to an oxygen-containing atmosphere, the heat treatment taking place at a temperature which is selected in such a way that the inequality [ Oi ] < [ Oi ] eq ⁢ ( T ) ⁢ exp ⁢ ( 2 ⁢ σ SiO 2 ⁢ Ω rkT ) is satisfied, where [Oi] is the oxygen concentration in the silicon wafer [Oi]eq(T) is the limit solubility of oxygen in silicon at a temperature T, &sgr;SiO2 is the surface energy of silicon dioxide &OHgr; is the volum

Abstract: There is provided a laminated type photoelectric converter whose sensitivity is enhanced uniformly. In the photoelectric converter in which a photoelectric conversion device is laminated above a signal transfer device, the sensitivity is enhanced by providing bends on a lower electrode of the photoelectric conversion device and by confining light uniformly.

Abstract: A solution for ruthenium chemical mechanical planarization containing a nitric acid and an oxidizer is disclosed. A method of forming ruthenium pattern using a polished ruthenium layer is also disclosed. The disclosed solution improves the polishing speed of ruthenium under low polishing pressure, reduces the dishing of ruthenium and decreases scratches generated in the interlayer insulating film. As a result, the disclosed solution and methods improve the techniques for device isolation and reduction of step coverage.