Abstract: A method for preventing burnt fuse pads from further electrical connection suitable before the formation of bumps on the wafer. A dielectric layer is formed over the active surface of the wafer covering the bump pads and the fuse pads of the wafer, wherein a central region of the fuse pads is burnt to form a gap which allows the material of the dielectric layer to fill up the gap. Afterwards, either a part of the dielectric layer is removed and the part of the dielectric layer covering the fuse pads remainsor a part of the dielectric layer covering the bump pads is removed. Then, an under ball metallurgy layer is formed on the bump pads of the wafer so that the material of the under ball metallurgy layer does not cover the two sides of the fuse pad at the same time, or fill into the gap. As a result, the electrical isolation still remains.

Abstract: The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

Abstract: The present invention provides a method for making an asymmetric inner structure in a contact or trench having a first sidewall, second sidewall, and a bottom in a semiconductor layer. A conformal dielectric layer is deposited on the interior surface of the contact or trench covering the first sidewall, second sidewall, and the bottom. A title angle ion implantation process is carried out to implant ions into the dielectric layer on the first sidewall and the bottom, but not the dielectric layer on the second sidewall. Thereafter, the doped dielectric layer on the first sidewall and the bottom is selectively etched away and leaving the un-doped dielectric layer on the second sidewall intact.

Abstract: A method for fabricating a capacitor of a semiconductor device is disclosed, in which it is possible to obtain reliability in an etch process, and to simplify manufacturing process steps.

Abstract: A ferroelectric capacitor encapsulation method for preventing hydrogen damage to electrodes and ferroelectric material of the capacitor. In general terms, the method for encapsulating a capacitor includes etching a bottom electrode of a capacitor to expose an underlying wafer surface. An undercut is etched between the capacitor and the wafer surface. The undercut is refilled with a barrier layer to reduce the diffusion of hydrogen from the surface of the wafer into the capacitor.

Abstract: Disclosed are a semiconductor device and a method for fabricating the same and, more particularly, a method for decreasing the size of semiconductor devices by stacking two substrates, one of which has only memory cells and the other of which has only logic circuits is disclosed. The disclosed method includes forming memory cells on a first semiconductor substrate; forming logic circuits on a second semiconductor substrate; and stacking the second semiconductor substrate on the first semiconductor substrate in order that the memory cells are electrically operable to the logic circuits on the second semiconductor substrate. In the disclosed stacked semiconductor substrate, the logic circuit area is placed on the memory cell area and these two areas are electrically connected by a metal interconnection, thereby decreasing the size of the semiconductor devices.

Abstract: In a method of forming a contact, a liner reactive ion etch is affected on a substrate to remove silicon nitride and silicon oxide. An oxygen plasma ex-situ clean, a Huang AB clean, and a dilute hydrofluric acid (DHF) clean are affected. Amorphous silicon is deposited and an anneal is performed to regrow and recrystallize amorphous silicon.

Abstract: A method of forming a deep trench DRAM cell on a semiconductor substrate has steps of: forming a deep trench capacitor in the semiconductor substrate; using silicon-on-insulator (SOI) technology to form a silicon layer on the deep trench capacitor; and forming a vertical transistor on the silicon layer over the deep trench capacitor, wherein the vertical transistor is electrically connected to the deep trench capacitor.

Abstract: A process for forming an organic semiconducting layer having molecular alignment. First, a photoalignment organic layer is formed on a substrate or A dielectric layer. Next, the photoalignment organic layer is irradiated by polarized light through a mask, such that the photoalignment organic layer becomes an orientation layer having molecular alignment. Finally, an organic semiconducting layer is formed on the orientation layer, such that the organic semiconducting layer aligns according to the alignment of the orientation layer to exhibit molecular alignment. The present invention can form an organic semiconducting layer with different molecular alignments in different regions over the same substrate by means of polarized light exposure through a mask.

Abstract: The invention encompasses a method of forming an insulative material along a conductive structure. A conductive structure is provided over a substrate, and an electrically insulative material is formed along at least a portion of the conductive structure. The electrically insulative material comprises at least one of SixOyNz and AlpOq, wherein p, q, x, y and z are greater than 0 and less than 10. A dopant barrier layer is formed over the electrically insulative material. BPSG is formed over the dopant barrier layer, and the dopant barrier layer prevents dopant migration from the BPSG to the electrically insulative material. The invention also encompasses transistor structures, and methods of forming transistor structures.

Abstract: A rough polysilicon film located on the upper surface of an interlayer film is removed by a CMP process, so that storage nodes and an embedded TEOS film are formed. The embedded TEOS film is removed concurrently with the interlayer film located in a memory cell region by etching. An opening end of a groove, the upper surface of the embedded TEOS film and the upper surface of the interlayer film are arranged on substantially the same plane. In the memory cell region and a peripheral circuit region, a substantially flat interlayer insulation film is obtained. This solves the problems of a step, falling and the like in a semiconductor device including a capacitor element.

Abstract: A simple method of forming a cup capacitor is disclosed. The method typically involves only “dry” deposition and etching steps, allowing applicants' method to be performed in a single processing apparatus, if so desired.

Abstract: The present invention discloses methods for fabricating a semiconductor device. In one embodiment, a conductive interconnection is formed on a semiconductor substrate to overlap with a mask insulating film pattern. An insulating film spacer is formed at side walls of the pattern, a high temperature oxide layer is formed on the resultant structure, and an interlayer insulating film is formed on the HTO film to planarize the surface of the resultant structure. Storage electrode and bit line contact holes are formed to expose the semiconductor substrate, by etching the interlayer insulating film according to a photolithography process using a contact mask. A landing plug poly is formed by depositing a conductive layer for a contact plug to fill up the contact holes.

Abstract: A method for producing antifuse structures and antifuses by which adjacent conductive regions can be selectively electrically connected involve the application of a sacrificial layer to a first conductive region. The sacrificial layer is patterned with the aid of a photolithographic method. A fuse layer is applied and the sacrificial layer is then removed. A non-conductive layer is applied and a conductive material is introduced in an opening in the non-conductive layer for the purpose of forming a second conductive region.

Abstract: The present invention provides methods of forming fuse box guard rings for integrated circuits and integrated circuit devices having the same. A fuse line is formed at a fuse portion of an integrated circuit device and a first insulating layer is formed on the fuse line. A guard ring pattern that encloses the fuse line is formed on the first insulating layer. A second insulating layer is formed on the guard ring pattern and the first insulating layer. The second insulating layer is partially etched to remove a portion of the second insulting layer in the fuse portion of the integrated circuit device enclosed by the guard ring pattern exposing a portion of the first insulating layer and to form a via hole in a peripheral circuit region of the integrated circuit device.

Abstract: A fabrication process and a structure of a laminated capacitor. A substrate is provided, and multiple electrode and dielectric layers, formed using high-speed physical metal deposition and dielectric material coating, respectively, are alternately stacked to form a laminated capacitor structure. In addition, a pair of terminal electrodes is formed on two sides of the electrode layers. The terminal electrodes are electrically connected to the electrode layers. A surface metallic layer is formed on the exposed surface of the terminal electrodes to prevent the surface from being oxidized. Thereby, the adhesion between the electrode layers and the dielectric layers is improved. The thickness uniformity ratio of the dielectric layers can be maintained at about ∈±10%. The relative displacement between two neighboring electrode layers can be smaller than about 100 microns to approach the standard capacitance required by the laminated capacitor.

Abstract: The invention encompasses a method of forming an insulative material along a conductive structure. A conductive structure is provided over a substrate, and an electrically insulative material is formed along at least a portion of the conductive structure. The electrically insulative material comprises at least one of SixOyNz and AlpOq, wherein p, q, x, y and z are greater than 0 and less than 10. A dopant barrier layer is formed over the electrically insulative material. BPSG is formed over the dopant barrier layer, and the dopant barrier layer prevents dopant migration from the BPSG to the electrically insulative material. The invention also encompasses transistor structures, and methods of forming transistor structures.

Abstract: A method for forming a group of structures in a semiconductor device includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, and forming an oxide layer over the conductive layer. The method further includes etching at least one opening in the oxide layer, filling the at least one opening with the conductive material, etching the conductive material to form spacers along sidewalls of the at least one opening, and removing the oxide layer and a portion of the conductive layer to form the group of structures.

Abstract: A method of fabricating a high aspect ratio deep trench having smooth sidewalls in a semiconductor substrate comprising a first etching step of contacting the substrate in which the deep trench is to be etched with either NF3 gas or SF6 gas in the absence of the other, followed by a second etching step with the etching gas of either NF3 or SF6 which ever one was not used in the first etching step, and alternating the first and second etching steps until the desired high aspect ratio trench depth is reached.

Abstract: Vertical capacitors are formed in a dielectric by a method that forms first and second electrodes spaced apart by a dielectric and substantially perpendicular to the surface of the dielectric. The capacitors may be formed in any dielectric level and are desirably planarized so that the capacitor plate and dielectric form a planar surface.