Patents Examined by Jesse Y Miyoshi
  • Patent number: 11322634
    Abstract: A method for forming a photovoltaic device comprising the steps of: providing a first conductive material on a substrate; depositing a continuous layer of a dielectric material less than 10 nm thick on the first conductive material; annealing the first conductive material and the layer of dielectric material; forming a chalcogenide light-absorbing material on the layer of dielectric material; and depositing a second material on the light-absorbing material such that the second material is electrically coupled to the light-absorbing material; wherein the first conductive material and the dielectric material are selected such that, during the step of annealing, a portion of the first conductive material undergoes a chemical reaction to form: a layer of a metal chalcogenide material at the interface between first conductive material and the dielectric material; and a plurality of openings in the layer of dielectric material; the openings being such to allow electrical coupling between the light-absorbing materia
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: May 3, 2022
    Assignee: NEWSOUTH INNOVATIONS PTY LIMITED
    Inventors: Xiaojing Hao, Fangyang Liu, Jialiang Huang, Chang Yan, Kaiwen Sun, Martin Andrew Green
  • Patent number: 11296139
    Abstract: An array substrate for a digital X-ray detector, and an X-ray detector including the same are disclosed, which reduce or minimize a contact resistance between a bias electrode and a PIN diode, and also improve a fill factor of the PIN diode. In the array substrate, a dual bias electrode in which a second bias electrode formed of a transparent conductive material is connected to a first bias electrode that is additionally connected to an upper electrode of the PIN diode, such that total resistance of the bias electrodes is reduced and a line width of the first bias electrode formed of a non-transparent material is reduced, resulting in an increased fill factor of the PIN diode.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 5, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Hyeji Jeon, Seungyong Jung, Hanseok Lee, Hyungil Na, Jungjune Kim
  • Patent number: 11282981
    Abstract: A light emitting diode pixel for a display including a substrate, a first LED sub-unit disposed on the substrate, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on at least one of the first and second LED sub-units, and vias formed in the substrate, in which each of the first to third LED sub-units comprises a first conductivity type semiconductor layer and a second conductivity type semiconductor layer, and each of the vias is electrically connected to at least one of the first, second, and third LED sub-units.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: March 22, 2022
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Chang Yeon Kim, Jong Hyeon Chae, Chung Hoon Lee, Seong Gyu Jang, Jong Min Jang, Ho Joon Lee
  • Patent number: 11257910
    Abstract: Provided is a semiconductor device, wherein: in a semiconductor substrate, a lifetime control region is provided from at least a part of a transistor portion to a diode portion; the transistor portion includes a main region, a boundary region located between the main region and the diode portion and overlapped with the lifetime control region, and a plurality of gate trench portions; the plurality of gate trench portions include a first gate trench portion provided in the main region and a second gate trench portion provided in the boundary region; and a gate resistance component of the first gate trench portion is different from a gate resistance component of the second gate trench portion.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: February 22, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Motoyoshi Kubouchi
  • Patent number: 11251335
    Abstract: A light emitting diode pixel for a display including a substrate, a first LED sub-unit disposed on the substrate, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on at least one of the first and second LED sub-units, and vias formed in the substrate, in which each of the first to third LED sub-units comprises a first conductivity type semiconductor layer and a second conductivity type semiconductor layer, and each of the vias is electrically connected to at least one of the first, second, and third LED sub-units.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: February 15, 2022
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Chang Yeon Kim, Jong Hyeon Chae, Chung Hoon Lee, Seong Gyu Jang, Jong Min Jang, Ho Joon Lee
  • Patent number: 11245091
    Abstract: The present disclosure provides an OLED panel, an OLED packaging method, and a display panel. The OLED panel includes a substrate; an OLED element on a surface of the substrate; an inorganic cover layer on the substrate and the OLED element, the inorganic cover layer being configured to cover a peripheral portion of the surface of the substrate; a bonding layer on the inorganic cover layer; and a barrier layer on the bonding layer, wherein a portion of the bonding layer on the peripheral portion includes at least one rib configured to form an airtight space for isolating the OLED element from the external.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 8, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Ang Xiao, Xiaodong Yang, Guowei Li, Quanqin Sun, Yangyang Zhang, Hongjian Wu, Chao Ma, Guanyu Lu
  • Patent number: 11244956
    Abstract: A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: February 8, 2022
    Assignee: SK hynix Inc.
    Inventors: In-Su Park, Jong-Gi Kim, Hai-Won Kim, Hoe-Min Jeong
  • Patent number: 11239154
    Abstract: In some embodiments, a fishbone structure in a power network includes a first conductive segment in a first conductive layer running in a first direction, a plurality of second conductive segments in a second conductive layer running in a second direction and a plurality of interlayer vias between the first conductive layer and the second conductive layer. The second direction is substantially vertical to the first direction. The plurality of second conductive segments overlap with the first conductive segment. The plurality of interlayer vias are formed at where the plurality of second conductive segments overlap with the first conductive segment. Each of the plurality of second conductive segments has a width such that the first conductive segment has a first unit spacing with a first adjacent conductive line or one of the plurality of second conductive segments has a second unit spacing with a second adjacent conductive line.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chien-Ju Chao, Fang-Yu Fan, Yi-Chuin Tsai, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 11227796
    Abstract: A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a multilayer cap layer and an ILD layer. A metal-filled via extends through the ILD layer and partially through the cap layer to make contact with the wiring line. There is a reliability enhancement material formed in one of the layers of the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: January 18, 2022
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Lawrence A. Clevenger, Baozhen Li, Xiao H. Liu, Kirk D. Peterson
  • Patent number: 11222994
    Abstract: A light emitting diode pixel for a display including a substrate, a first LED sub-unit disposed on the substrate, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on at least one of the first and second LED sub-units, and vias formed in the substrate, in which each of the first to third LED sub-units comprises a first conductivity type semiconductor layer and a second conductivity type semiconductor layer, and each of the vias is electrically connected to at least one of the first, second, and third LED sub-units.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: January 11, 2022
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Chang Yeon Kim, Jong Hyeon Chae, Chung Hoon Lee, Seong Gyu Jang, Jong Min Jang, Ho Joon Lee
  • Patent number: 11217640
    Abstract: Disclosed is a transparent display apparatus. The transparent display apparatus includes a first substrate including a plurality of pixel areas, a first partition wall surrounding each of the plurality of pixel areas, a filling layer covering the first partition wall and the plurality of pixel areas, and a second substrate coupled to the filling layer. Accordingly, a stress applied to a display panel is reduced, and the peeling of an organic light emitting device and transmission of water are preventing from being spread, thereby enhancing the reliability of the display panel.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: January 4, 2022
    Assignee: LG Display Co., Ltd.
    Inventor: Hyunju Jung
  • Patent number: 11211436
    Abstract: A display device includes: an insulating layer defining a pixel region with a first extending portion and a second extending portion, the first extending portion extending in a direction along a first side of the pixel region, the second extending portion extending in a direction along a second side of the pixel region, the second side crossing the first side; and an organic electroluminescent layer formed in the pixel region, on the first extending portion, and on the second extending portion. A width of the first extending portion in a plan view is smaller than a width of the second extending portion.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: December 28, 2021
    Assignee: Japan Display Inc.
    Inventor: Kenta Hiraga
  • Patent number: 11211591
    Abstract: An organic light-emitting display device including an encapsulating layer covering a light-emitting element and an encapsulating substrate on the encapsulating layer is provided. The organic light-emitting display device may include metal particles which are dispersed on an outer surface of the encapsulating substrate having a high thermal conductivity, so that damage of the light-emitting element due to external impact may be prevented. And, the organic light-emitting display device may include a capping layer covering the metal particles, so that the surface roughness due to the metal particles may be reduced.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: December 28, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Jung-Mook Kim, Young-Hoon Shin
  • Patent number: 11205671
    Abstract: A solid-state image sensor including a semiconductor substrate having photoelectric conversion elements being two-dimensionally formed therein, and a color filter layer formed on the semiconductor substrate and having color filters of colors being two-dimensionally formed therein in a pattern such that the color filters correspond respectively to the photoelectric conversion elements. The color filter layer satisfies formulas (1) and (2): 200?A?700??(1) C?A+200??(2) where A represents a thickness in nm of a first-color color filter of a first color among the colors, and C represents a thickness in nm of color filters of colors other than the first color.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 21, 2021
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Tomohiro Imoto, Satoshi Takahashi
  • Patent number: 11201271
    Abstract: A method for manufacturing a light emitting device includes: forming a first reflector that covers outer peripheral faces of a light transmissive member; forming a light guiding member covering at least a portion of the light transmissive member, a portion of a lower face of the first reflector, and at least some portions of lateral faces of a light emitting element disposed under the light transmissive member; and forming a second reflector covering a portion of the lower face of the first reflector that is exposed from the light guiding member and located outward of the light guiding member.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: December 14, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Tadao Hayashi, Teruhito Azuma
  • Patent number: 11201211
    Abstract: A method of manufacturing a super junction structure includes etching a material to define a trench, wherein the trench has a tapered profile. The method further includes implanting dopants into sidewalls and a bottom surface of the trench to define a doped region, wherein the doped region surrounds the trench. The method further includes depositing an undoped material into the trench. The method further includes performing a thermal process, wherein the thermal process drives the dopants from the doped region into the undoped material to form a conductive pillar in the trench.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shuai Zhang, Lian-Jie Li, Zhong-Hao Chen, Feng Han, Jian Wu
  • Patent number: 11189714
    Abstract: Embodiments of the present disclosure provide a method of cleaning a lanthanum containing substrate without formation of undesired lanthanum compounds during processing. In one embodiment, the cleaning method includes treating the lanthanum containing substrate with an acidic solution prior to cleaning the lanthanum containing substrate with a HF solution. The cleaning method permits using lanthanum doped high-k dielectric layer to modulate effective work function of the gate stack, thus, improving device performance.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chi Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11183620
    Abstract: A light emitting diode having a plurality of light emitting cells is provided. The light emitting diode according to an exemplary embodiment includes a lower insulation layer covering an ohmic reflection layer, connectors disposed on the lower insulation layer to connect the light emitting cells, and an upper insulation layer covering the connectors and the lower insulation layer. An edge of the lower insulation layer is spaced apart farther from an edge of the upper insulation layer than an edge of the light emitting cell. The lower insulation layer susceptible to moisture may be protected and reliability of the light emitting diode may improve.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 23, 2021
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Se Hee Oh, Hyun A Kim, Jong Kyu Kim, Jong Hyeon Chae
  • Patent number: 11177413
    Abstract: A light emitting diode pixel for a display including a substrate, a first LED sub-unit disposed on the substrate, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on at least one of the first and second LED sub-units, and vias formed in the substrate, in which each of the first to third LED sub-units comprises a first conductivity type semiconductor layer and a second conductivity type semiconductor layer, and each of the vias is electrically connected to at least one of the first, second, and third LED sub-units.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: November 16, 2021
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Chang Yeon Kim, Jong Hyeon Chae, Chung Hoon Lee, Seong Gyu Jang, Jong Min Jang, Ho Joon Lee
  • Patent number: 11177447
    Abstract: A method for manufacturing a flexible display includes forming a coating film. Forming the coating film includes depositing a high rigidity material layer on a substrate and forming a transfer layer on the high rigidity material layer. The coating film is bonded to a display surface of a display panel by the transfer layer. The substrate is removed after the coating film is bonded to the display surface of the display panel.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: November 16, 2021
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Fei-Lin Yang, Bin-Yi Lin, Yang-Po Chiu