Abstract: Some embodiments relate to a device disposed on a semiconductor substrate. The semiconductor substrate includes a base region and a crown structure extending upwardly from the base region. The crown structure is narrower than the base region. A plurality of fins extend upwardly from an upper surface of the crown structure. A gate dielectric material is disposed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode is disposed along sidewall portions of the gate dielectric material. An uppermost surface of the conductive electrode resides below the upper surfaces of the plurality of fins.

Abstract: Embodiments of the present invention provide improved methods and structures for fabrication of capacitor-less DRAM devices, sometimes referred to as ZRAM devices. A channel is formed in a fin-type field effect transistor (finFET) that is comprised of a finned channel portion and a convex channel portion. The finned channel portion may be comprised of a first semiconductor material and the convex channel portion may be comprised of a second, different semiconductor material. In embodiments, a metal gate is disposed around the elongated surface of the channel region, but is not disposed on the short surface of the channel region. A first spacer is disposed adjacent to the gate and in direct physical contact with the short surface of the channel region, and a second spacer is disposed adjacent to the first spacer.

Abstract: An organic light emitting diode display device is discussed. The organic light emitting diode display device includes pixels including an organic light emitting diode, and a bank partitioning the pixels which are neighboring, and having openings exposing at least a portion of a first electrode of the organic light emitting diode allocated for each of the pixels. The bank includes at least one groove provided between the neighboring pixels in at least one area.

Abstract: An electronic circuit includes a noise source and an analog circuit and a logic circuit that may be adversely affected by noise. At least a portion of the analog circuit and the logic circuit is formed on a buried impurity layer whose conductivity is different from that of a substrate, and at least a portion of the periphery of that portion is surrounded by an impurity layer that is different from the substrate. Thus, propagation of the noise from the noise source is prevented.

Abstract: The present disclosure relates to a method of depositing a fluid onto a substrate. In some embodiments, the method may be performed by mounting a substrate to a micro-fluidic probe card, so that the substrate abuts a cavity within the micro-fluidic probe card that is in communication with a fluid inlet and a fluid outlet. A first fluidic chemical is selectively introduced into the cavity via the fluid inlet of the micro-fluidic probe card.

Abstract: The present disclosure provides HKMG transistor structures and fabrication methods thereof. An exemplary method includes providing a base substrate having a first region and a second region; forming a dielectric layer having a first opening in the first region and a second opening in the second region over; forming a gate dielectric layer on a side surface of the first opening and a portion of the base substrate in the first opening and on a side surface of the second opening and a portion of the base substrate in the second opening; filling a sacrificial layer in the first opening; forming a second work function layer in the second opening and a second gate electrode layer on the second work function layer; removing the sacrificial layer; and forming a first work function layer in the first opening and a first gate electrode layer on the first work function layer.

Abstract: Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.

Abstract: A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

Abstract: A system includes a stress-engineered substrate comprising at least one tensile stress layer having a residual tensile stress and at least one compressive stress layer having a residual compressive stress. The at least one tensile layer and the at least one compressive layer are coupled such that the at least one tensile stress layer and the at least one compressive stress layer are self-equilibrating. At least one functional device is disposed on the stress-engineered substrate. The stress-engineered substrate is configured to fracture in response to energy applied to the substrate. Fracturing the stress-engineered substrate also fractures the functional device. The system includes at least one decoy device. Fragments of the decoy device are configured to obscure one or more physical characteristics of the functional device and/or one or more functional characteristics of the functional device after the functional device is fractured.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method is performed by forming a gate structure over a substrate, and selectively implanting the substrate according to the gate structure to form first and second source/drain regions on opposing sides of the gate structure. A first MEOL structure is formed on the first source/drain region and a second MEOL structure is formed on the second source/drain region. The first MEOL structure has a bottommost surface that extends in a first direction from directly over the first source/drain region to laterally past an outermost edge of the first source/drain region. A conductive structure is formed to contact the first MEOL structure and the second MEOL structure. The conductive structure laterally extends from directly over the first MEOL structure to directly over the second MEOL structure along a second direction perpendicular to the first direction.

Abstract: An ultra-fine pattern deposition apparatus can include a base substrate; a photothermal converter disposed on or in the base substrate and configured to convert optical energy into thermal energy; a source part disposed on the photothermal converter; and a light reflector configured to reflect light based on a refractive index difference between the light reflector and the base substrate, and guide a source material emitted from the source part to a target region based on an opening in the light reflector and the photothermal converter being heated with the thermal energy from the photothermal converter, in which the opening in the light reflector includes a laterally recessed lower part and an upper part protruded from the laterally recessed lower part, and the laterally recessed lower part is between the upper part and the base substrate, and the photothermal converter is disposed between base substrate and the source part.

Abstract: A semiconductor device structure comprises stacked tiers each comprising at least one conductive structure and at least one insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and at least one opening extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. The at least one conductive structure of each of the stacked tiers extends continuously from at least one of the steps of the at least one staircase structure and around the at least one opening to form at least one continuous conductive path extending completely across each of the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.

Abstract: Disclosed is a display apparatus. The display apparatus includes a substrate, a first wiring part on the substrate, a first insulation layer on the first wiring part, a microchip on the first insulation layer, a second wiring part on the microchip, and an organic light emitting device on the second wiring part. The microchip includes a first surface and a second surface opposite to each other, a first pad part on the first surface, and a second pad part on the second surface. The first pad part is connected to the first wiring part, and the second pad part is connected to the second wiring part.

Abstract: A carbon conductive structure includes: first graphenes of a graphene plug which are stacked in a plurality of layers along a vertical direction; and second graphenes of a graphene wiring line which are stacked in a plurality of layers along the vertical direction, wherein edge portions of the first graphenes and edge portions of the second graphenes are electrically connected to each other.

Abstract: A semiconductor apparatus 1 includes a circuit substrate 3 having a circuit pattern layer 3c on an upper principal surface, semiconductor elements 4a and 4b mounted on the circuit pattern layer 3c of the circuit substrate 3, a printed substrate 6 arranged apart from the circuit substrate 3 on the upper principal surface side of the circuit substrate 3, a housing 2 mold-sealing the upper principal surface side of the circuit substrate 3, and a block 10 provided sandwiching at least part of the housing 2 and being opposite to the circuit substrate 3, the block having a linear expansion coefficient smaller than that of the housing 2.

Abstract: Some embodiments include apparatuses and methods having a node to receive ground potential, a first diode including an anode coupled to the node, a second diode including an anode coupled to the node, a first circuit to apply a voltage to a cathode of each of the first and second diodes to cause the first and second diodes to be in a forward-bias condition, and a second circuit to generate a signal having a duty cycle based on a first voltage across the first diode and a second voltage across the second diode. At least one of such the embodiments includes a temperature calculator to calculate a value of temperature based at least in part on the duty cycle of the signal.

Abstract: The present disclosure relates to a high voltage transistor device having a thin polysilicon film field plate, and an associated method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed between source and drain regions and separated from a substrate by a gate dielectric. A spacer is disposed along an upper surface of the substrate. The spacer extends along a first gate sidewall closer to the drain region, crosses over an upper edge of the gate electrode, and further extends laterally to cover a portion of an upper surface of the gate electrode. A field plate including a polysilicon thin film is disposed along upper and sidewall surfaces of the spacer so that the polysilicon thin film is separated from the gate electrode and the substrate by the spacer. The thin polysilicon film field plate improves the breakdown voltage of the transistor device.

Abstract: A microphone packaging assembly (100) provides a printed circuit board (pcb) (106) for coupling to a microphone device (102) having a bottom acoustic port (104). The pcb provides an acoustic port opening (108) which aligns with the bottom acoustic port (104) of the microphone device (102). A solder pad pattern (110) is disposed on the pcb (106). The solder pad pattern (110) is configured to provide both electrical connection (114) and an incomplete solder seal (116) having purposeful acoustic leak to the microphone device (102). A conformable coating (126) provides a seal to the purposeful acoustic leak. A single acoustic test can be performed to detect proper environmental protection and acoustic sealing of the packaged assembly (100).

Abstract: Embodiments of the present disclosure provide a method of cleaning a lanthanum containing substrate without formation of undesired lanthanum compounds during processing. In one embodiment, the cleaning method includes treating the lanthanum containing substrate with an acidic solution prior to cleaning the lanthanum containing substrate with a HF solution. The cleaning method permits using lanthanum doped high-k dielectric layer to modulate effective work function of the gate stack, thus, improving device performance.

Abstract: According to an exemplary embodiment, a display substrate includes a gate metal pattern comprising a gate electrode, an active pattern disposed on the gate pattern and a source metal pattern disposed on the active pattern. The source metal pattern includes a first lower pattern disposed on the active pattern, a second lower pattern disposed on the first lower pattern, a low-resistance metal pattern disposed on the second lower pattern, and an upper pattern disposed on the low-resistance metal pattern. The first lower pattern, the second lower pattern, and the upper pattern each include a material that is the same.