Abstract: A conditional construction container (CCC) provides seamless restore operation during abort event. During normal restore, the CCC assumes a hold state, wherein data blocks are sent from the backup source to the restore host directly. When interrupt occurs, the CCC assumes compression mode, wherein the CCC compresses the data blocks and stores the compressed blocks in memory allocated to the CCC. When the restore operation can resume, the backup agent instructs the CCC to begin data reconstruction operation and the CCC will assume busy mode no longer accepting new data blocks. During the busy state the CCC decompresses the compressed data blocks from the container and reconstruct the original data onto the restore host. Since the container constructed in the memory allocated to the CCC contain data that was obtained upon the interrupt, the restore operation resumes by reconstructing the data from the point of the interrupt seamlessly.

Abstract: Various embodiments include at least one of systems, methods, and software to receive input configuring tests within a computing environment to expose users to standard application or website experiences or test experiences. In some embodiments, multiple tests may be configured to run orthogonally within user experiences without affecting the results of one another. Some such embodiments preserve the ability to execute certain tests in a non-orthogonal manner while other tests are allowed to execute orthogonally.

Abstract: A hardware queue for an integrated circuit device includes an internal queue memory and at least one external queue memory. The internal queue memory and the external queue memory are operated as a continuous hardware queue memory by monitoring occupancy of the internal queue memory and, based on that occupancy, controlling an internal tail pointer indicating a next write point for inserting new data into the internal queue memory, an internal head pointer indicating a next read point for extracting data from the internal queue memory based on order of insertion, at least one external tail pointer indicating a next write point for inserting new data into the external queue memory, at least one external head pointer indicating a next read point for extracting data from the external queue memory based on order of insertion, and wrap pointers indicating transitions between the internal queue memory and the external queue memory.

Abstract: An interconnect apparatus comprises first node circuitry for performing first node operations to service data access requests in respect of a first range of memory addresses and second node circuitry for performing second node operations to service data access requests in respect of a second range of memory addresses. The interconnect comprises interface circuitry to: receive a retry indication in respect of a data access request from the first node and forward the retry indication to the requester circuitry; responsive to determining that the interface circuitry has capacity for the data access request, transmit a reissue capacity message to the requester circuitry; receive a reissued data access request from the requester circuitry; and issue the reissued data access request to the second node circuitry. The second node circuitry is responsive to receiving the reissued data access request to service the data access request.

Abstract: A data transmission circuit includes a data bus inversion encoding circuit configured to compare previous output data and current output data, invert or non-invert the current output data to control the number of data transitions; and transmitters configured to drive signal transmission lines based on outputs of the data bus inversion encoding circuit.

Abstract: Computing architectures, platforms, and systems are provided herein. In one example, a system is provided. The system includes a communication arrangement for peripheral component interconnect express (PCIe) traffic transferred over a communication fabric. The communication arrangement establishes an expanded address that provides a quantity of port identifiers to a host greater than indicated by a quantity of bits in a port field of the PCIe traffic, where the expanded address employs one or more bits of the PCIe traffic other than the port field. The communication arrangement detects a transfer among the PCIe traffic issued by the host having the expanded address corresponding to a destination. Based on the expanded address, the communication arrangement identifies routing information to route the transfer over the communication fabric to the destination.

Abstract: The described technology is generally directed towards accelerating data handling in a cloud data storage system by using smart network interface cards (SmartNICs) at the nodes. Instead of copying data to kernel space, many input/output (I/O) operations can be handled primarily by the SmartNIC, using the SmartNIC's memory. For example, mirrored data writes can be sent directly from the SmartNIC's memory associated with the node handling the write to other nodes, without first copying the data to kernel space. Object reads can be handled at a node by having segments of the object queued, in order, in the node's associated SmartNIC's memory, and sent to a requesting client without having to be copied to the handling node's kernel space, unless low memory conditions exist in the SmartNIC's memory.

Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.

Abstract: Methods and systems are described for receiving a set of input bits at a plurality of drivers and responsively generating an ensemble of signals, each respective signal of the ensemble of signals generated by receiving a subset of input bits at a respective driver connected to a respective wire of a multi-wire bus, the received subset of bits corresponding to sub-channels associated with the respective wire, generating a plurality of weighted analog signal components, each weighted analog signal component (i) having a corresponding weight and sign selected from a set of wire-specific sub-channel weights associated with the respective wire and (ii) modulated by a corresponding bit of the received subset of bits, and generating the respective signal by forming a summation of the plurality of weighted analog signal components at a common node connected to the respective wire for transmission over the respective wire of the multi-wire bus.

Abstract: A computer-implemented method, according to one approach, includes: receiving a first request to perform a write operation from a host, and performing the write operation. Metadata corresponding to the first request is sent to the secondary data storage device, and metadata corresponding to a second request to perform the write operation is received from the secondary data storage device, where the second request was received at the secondary data storage device from the host. The metadata corresponding to the first and second requests is used to determine whether the write operation has been mirrored across the primary and secondary data storage devices. In response to determining that the write operation has been mirrored across the primary and secondary data storage devices, a response is sent to the secondary data storage device which indicates that the write operation has been reconciled across the primary and secondary data storage devices.

Abstract: A method for performing backup operations includes identifying a plurality of virtual machines (VMs) to back up, grouping the plurality of VMs to obtain a plurality of VM groups, and initiating a configuration of a production agent on a production host associated with a first VM group of the plurality of VM groups, wherein the configured first production agent initiates a backup operation on at least the first VM group.

Abstract: Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines.

Abstract: In one aspect, implementing enhanced QoS for multiple replication sessions in a replication setup includes, for each of a number of replication sessions simultaneously implemented via the storage system, determining an assigned priority level and calculating a corresponding resource profile. The resource profile specifies a minimum required amount of bandwidth and a minimum amount of input/output (IO) operations for the replication session. An aspect also includes determining available system resources for an aggregate of the replication sessions. The available system resources indicate a maximum available amount of bandwidth and a maximum available IO rate across the storage system. An aspect further includes apportioning resources among the replication sessions as a function of collective priority levels, resource profiles, and the available system resources.

Abstract: In one aspect, extent lock resolution for storage devices includes designating one of the storage devices as a lock winner, which takes priority over another storage device over a lock. An aspect also includes receiving a replication request issued, by a host during active/active replication, determining an extent of pages to be modified by the request, locking the extent in local storage device, and executing the request at the local device. An aspect also includes sending a write request to a remote device. If the remote device is the designated lock winner, and an attempt to lock the extent is unsuccessful, the remote device waits for the lock to become available. If the remote device is not the designated lock winner, and an attempt to lock the extent is unsuccessful, the remote device rejects the write request and sends a request to the local device to resend the write request.

Abstract: A storage device includes a memory and a controller. The controller controls the memory such that, in response to a request for a first read operation on the memory while a first write operation is performed on the memory, the first write operation is suspended, and the first read operation is performed, the suspended first write operation is resumed after the first read operation is completed, and second write operation subsequent to the first write operation is performed on the memory after the resumed first write operation is completed. The controller throttles an amount of data communicated to the memory device for the second write operation or for a second read operation subsequent to the first read operation, based on a frequency that the first write operation is suspended.

Abstract: The present invention relates to a data processing method, including the steps of intercepting a signal within a communications channel between a predefined peripheral device for a computing system and an application executing on the computing system and processing the signal and performing one or more actions in response to the processing. At least one action affects onward transmission of one or more signals within the communications channel. A data processing system is also described.

Abstract: A method for providing logical block address (LBA) to physical block address (PBA) binding in a storage device includes: receiving at least one thread at a hardware engine of the device controller of the storage device, each thread including data and LBAs for the data; writing the data into a write buffer of the storage device; binding, by the hardware engine of the device controller, a sequence of contiguous PBAs for a section of the memory to the LBAs for the data in the write buffer; determining if the write buffer contains enough data for the section of the memory; and if the write buffer contains enough data for the section of the memory, writing the data to the section of the memory.

Abstract: In one aspect of the present description, in an input/output (I/O) device having multiple CPUs and multiple I/O ports, a cycle of I/O port rotations is initiated in which each port rotation of the cycle includes rotating an assignment of at least one I/O port from one CPU to a different CPU of a plurality of the CPUs. In the illustrated embodiment, an I/O port assignment for each CPU of the plurality CPUs is rotated for at least a portion of the cycle. Other features and aspects may be realized, depending upon the particular application.

Abstract: High-efficiency control technology for non-volatile memory. A controller allocates spare blocks of a non-volatile memory to provide an active block and writes data issued by a host to the active block. The controller further uses the active block as the destination for data transferred from a first source block when there are fewer spare blocks than the threshold amount. When a second source block meets the transfer requirements, the controller uses the active block as the destination for data transferred from the second source block.

Abstract: An example method can include, responsive to receiving a sanitization command, performing a deterministic garbage collection operation on a memory. The deterministic garbage collection operation performed on the memory can result in physical erasure of all invalid data stored on the memory without losing valid data stored on the memory.