Abstract: Computing architectures, platforms, and systems are provided herein. In one example, a computing system is provided. The computing system includes a management processor configured to initiate a peripheral component interconnect express (PCIe) arrangement between a host processor and a plurality of PCIe devices over a PCIe fabric comprising one or more PCIe switches. The PCIe arrangement is established to detect a data transfer directed to an expanded address of a greater length than a destination field of the PCIe communications of the detected data transfer by using at least another portion of the PCIe communications to store a portion of the expanded address that is in excess of the length than the destination field of the PCIe communications, and route the detected data transfer over the PCIe fabric to a destination device associated with the expanded address.

Abstract: Systems, methods, and apparatuses relating to in-network storage for a configurable spatial accelerator are described.

Abstract: A location of a log file is determined, wherein data corresponding to writes is written sequentially starting from a starting block of the log file. A determination is made in the log file of a range of blocks in which data corresponding to a next write is anticipated to be written. Preprocessing operations are performed corresponding to the range of blocks of the log file in which the data corresponding to the next write is anticipated to be written.

Abstract: A system and method for efficiently scheduling requests. In various embodiments, a processor sends commands such as read requests and write requests to an arbiter. The arbiter reduces latencies between commands being sent to a communication fabric and corresponding data being sent to the fabric. When the arbiter selects a given request, the arbiter identifies a first subset of stored requests affected by the given request being selected. The arbiter adjusts one or more attributes of the first subset of requests based on the selection of the given request. In one example, the arbiter replaces a weight attribute with a value, such as a zero value, indicating the first subset of requests should not be selected. Therefore, during the next selection by the arbiter, only the requests in a second subset different from the first subset are candidates for selection.

Abstract: Systems and methods for predicting read commands and pre-fetching data when a memory device is receiving random read commands to non-sequentially addressed data locations are disclosed. A limited length search sequence of prior read commands is generated and that search sequence is then converted into an index value in a predetermined set of index values. A history pattern match table having entries indexed to that predetermined set of index values contains a plurality of read commands that have previously followed the search sequence represented by the index value. The index value is obtained via application of a many-to-one algorithm to the search sequence. The index value obtained from the search sequence may be used to find, and pre-fetch data for, a plurality of next read commands in the table that previously followed a search sequence having that index value.

Abstract: A USB power-delivery device includes a clock signal generator which stops generation of a clock signal for a dual-role port (DRP) while the USB power-delivery device operates in a low power mode until an attach event occurs, and starts the generation of the clock signal for the DRP after the attach event occurs.

Abstract: The present subject disclosure provides a switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.

Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

Abstract: A data storage device includes a storage medium; a buffer memory configured to temporarily store data to be inputted to, or outputted from, the storage medium; and a controller configured to control data exchange with the storage medium, allocate a write tag to a write command, and change an attribute of the write tag according to a processing status of the write command.

Abstract: Various embodiments include at least one of systems, methods, and software to receive input configuring tests within a computing environment to expose users to standard application or website experiences or test experiences. In some embodiments, multiple tests may be configured to run orthogonally within user experiences without affecting the results of one another. Some such embodiments preserve the ability to execute certain tests in a non-orthogonal manner while other tests are allowed to execute orthogonally.

Abstract: Methods of operating a serial data bus generate two-level bridge symbols to insert between four-level symbols on one or more data lanes of the serial data bus, to reduce voltage deltas on the one or more data lanes during data transmission on the serial data bus.

Abstract: A communications interface for interfacing between a host system and a state machine, the communications interface comprising: an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.

Abstract: Systems, devices, methods, and techniques for bus receivers operable to provide a data output corresponding to a voltage differential provided on a two-conductor data bus. In one example, a bus receiver comprises a four-quadrant input circuit and a gain stage coupled to the four-quadrant input circuit. In various examples, the four-quadrant input circuit is operable to provide common mode current compensation based on a common mode voltage present on the two-conductor data bus.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating a disaggregated computing architecture is presented. The method includes, receiving user commands to establish compute units among a plurality of physical computing components, each of the compute units comprising one or more of the plurality of physical computing components selected from among central processing units (CPUs), graphics processing units (GPUs), storage modules, and network interface modules. The method also includes forming the compute units based at least on logical partitioning within a Peripheral Component Interconnect Express (PCIe) fabric communicatively coupling the plurality of physical computing components, wherein each of the compute units have visibility over the PCIe fabric to the one or more of the plurality of physical computing components assigned to the associated compute units using the logical partitioning within the PCIe fabric.

Abstract: The described technology is generally directed towards accelerating data handling in a cloud data storage system by using smart network interface cards (SmartNICs) at the nodes. Instead of copying data to kernel space, many input/output (I/O) operations can be handled primarily by the SmartNIC, using the SmartNIC's memory. For example, mirrored data writes can be sent directly from the SmartNIC's memory associated with the node handling the write to other nodes, without first copying the data to kernel space. Object reads can be handled at a node by having segments of the object queued, in order, in the node's associated SmartNIC's memory, and sent to a requesting client without having to be copied to the handling node's kernel space, unless low memory conditions exist in the SmartNIC's memory.

Abstract: A portable computer-peripheral apparatus comprises a Universal Serial Bus (USB) connector. The apparatus is operable to communicate with a computer terminal (e.g. a ‘PC’). Following connection to the PC, the apparatus initialises (i.e. presents or enumerates itself) as a HID keyboard and then sends to the terminal a first predefined sequence of keycodes automatically without manual interaction; the keycodes complying with the human interface device (HID) keyboard standard protocol. Each keycode represents and simulates a keystroke, such as those performed when a user strikes a key on the PC keyboard. The keycode sequence automates the direct access to content, and/or or the initiation of a task or other process.

Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.

Abstract: A redundancy termination panel includes first and second interfaces configured to be coupled to first and second I/O modules, respectively. The redundancy termination panel also includes a third interface configured to be coupled to a field device. The redundancy termination panel further includes an I/O channel circuit associated with an I/O channel between the I/O modules and the field device. The I/O channel circuit is configured to allow an input current used for receiving data from the field device to be split such that different portions of the input current are sourced by different ones of the I/O modules. The I/O channel circuit is also configured to combine multiple currents driven by different ones of the I/O modules and provide an output current used for sending data to the field device.

Abstract: A memory management method is provided. The method includes storing an acquired first command into a command queue, and setting a command phase value of the first command according to a current command phase, wherein in response to determining that the first command is a flush command, calculating a command phase count value corresponding to the current command phase, and adjusting the current command phase; selecting a new target command from the command queue, and executing the target command according to a target command phase value of the target command and a corresponding target command phase count value, wherein the target command phase count value which is not a preset value is adjusted; determining, according to the adjusted target command phase count value, whether to respond to a host system that an execution of a target flush command corresponding to the target command phase value is completed.

Abstract: A data transmission circuit includes a data bus inversion encoding circuit configured to compare previous output data and current output data, invert or non-invert the current output data to control the number of data transitions; and transmitters configured to drive signal transmission lines based on outputs of the data bus inversion encoding circuit.