Abstract: Apparatus and methods structured with respect to a data bus having a number of data lines and a number of shield lines can be implemented in a variety of applications. Such apparatus and methods can include driver and receiver circuits that operate to generate and/or decode a data bit inversion signal associated with data propagated on data lines of the data bus. The driver and receiver circuits may be arranged to operate on a two bit basis to interface with the data bus having data lines grouped with respect to the two bits with shield lines for the respective two bit data lines.

Abstract: Microelectronic package communications are described that use radio interfaces that are connected through waveguides. One example includes an integrated circuit chip, a package substrate to carry the integrated circuit chip, the package substrate having conductive connectors to connect the integrated circuit chip to external components, and a radio on the package substrate coupled to the radio chip to modulate the data over a carrier and to transmit the modulated data. A waveguide connector is coupled to a dielectric waveguide to receive the transmitted modulated data from the radio and to couple it into the waveguide, the waveguide carries the modulated data to an external component.

Abstract: A data transfer device including a buffer unit configured to temporarily store transfer data that is transferred to a common bus, a write control unit configured to write input data as the transfer data to the buffer unit, a read control unit configured to read the transfer data from the buffer unit, an interface unit configured to transfer the transfer data to the common bus according to a predetermined bus protocol, the transfer data being read from the buffer unit by the read control unit, and a band-smoothing unit configured to smooth a band of the common bus by switching between the time intervals between pieces of the transfer data based on a position of the transfer data in a frame image, during a period when the transfer data is transferred to the common bus based on a position of the transfer data in a frame image.

Abstract: A circuit inhibits single-ended analogue signal noises and can be included in a terminal accessory. The circuit includes an input interface module, a differential amplification module, an analogue signal processing module, an isolation module and a control module, wherein the input interface module at least includes an analogue signal line and a digital signal line, the differential amplification module includes differential input ends and an output end; the analogue signal line and the digital signal line of the input interface module are respectively connected to the differential input ends of the differential amplification module, so that the analogue signal line and the digital signal line form a pseudo-differential pair, and the output end of the differential amplification module is connected to the analogue signal processing module; the digital signal line is further connected to the isolation module, and the isolation module is further connected to the control module.

Abstract: Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions. Previously encoded portions may be used when succeeding frames have a level of motion less than a threshold. In such case, all or part of succeeding frames may not be encoded, increasing bandwidth and speed in some embodiments.

Abstract: A switch card and a server are provided. The switch card is adapted to couple a riser card and a hard drive array, and includes a storage device, a processing circuit, a first connection portion, and a plurality of first sub-connection portions. When the first connection portion is coupled to the riser card, the processing circuit receives a setting signal of the riser card via the first connection portion. The processing circuit reads a configuration table stored in the storage device according to the setting signal. When the first sub-connection portions are coupled to a plurality of second sub-connection portions of the hard drive array, the second sub-connection portions are coupled to a plurality of hard drives of the hard drive array via a plurality of first cables. The processing circuit determines a configuration setting between the first cables and the hard drives according to the configuration table.

Abstract: A signal transmitter of the invention is coupled to a plurality of signal receivers by a bus, and is configured to transmit display data through the bus for displaying a line. The signal transmitter includes a first data sequence and a second data sequence. The first data sequence has an electronic characteristic of a first value and is transmitted to a first signal receiver of the signal receivers, and the second data sequence has the electronic characteristic of a second value and is transmitted to a second signal receiver of the signal receivers. Wherein, a first signal transmission path from the signal transmitter to the first signal receiver is shorter than a second signal transmission path from the signal transmitter to the second signal receiver, and the first value is larger than the second value.

Abstract: Embodiments of the present technology presented herein relate to a method for configuring a remote node and to a host node for performing said configuring of the remote node. The present technology presented herein also generally relates to embodiments of a method for reconfiguring the host node and to a reconfigurable host node. More particularly, the embodiments presented herein relate to configuring the remote node and reconfiguring the host by duplicating Peripheral Component Interconnect express, PCIe, hot-plug elements such that they are present at both the host node and the remote node. Furthermore there is introduced a connection state indicator at both the host node and the remote node for indicating that an optical connection has been established between the host and remote node.

Abstract: An apparatus to arbitrate data transfer between a computing host and a storage device across an interface includes a data transfer limiter configured to track an amount of data credits used by a data transfer across the interface and an amount of accrued data credits available to the interface. The apparatus further includes a data transfer arbiter configured to selectively disable the data transfer across the interface when the amount of data credits used by the data transfer across the interface exceeds a first threshold, and to selectively enable the data transfer across the interface when the amount of data credits used by the data transfer across the interface does not exceed a second threshold. The amount of accrued data credits reduces the amount of data credits used by the data transfer.

Abstract: Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.

Abstract: Provided is a plant equipment state gathering system which simplifies the work relating to attaching and/or replacing a detection device that detects the state of plant equipment. A plant equipment state gathering system is provided with a detection device, a mobile terminal, a network construction device and a data storage device. The detection device includes a tag unit that can store, in a non-contact manner, at least some setting information that at least includes network information for connecting to the network from the mobile terminal. The mobile terminal includes a tag control unit that allows the tag unit of the detection device to automatically store, in a non-contact manner, at least some of the setting information. When network information is stored in the tag unit of the detection device by the mobile terminal the network construction device uses this network information to determine whether to allow the connection of the detection device to the network.

Abstract: An information switch comprises a plurality of input circuits and a plurality of output circuits, the information switch being configured to communicate information units between the input circuits and the output circuits in successive transmission cycles; each input circuit being configured, in dependence upon a queue of one or more information units for transmission via that input circuit and in dependence upon hint data received in respect of a current transmission cycle, to send an information unit transmission request to one or more of the output circuits; and each output circuit being configured, in response to one or more information unit transmission requests received from respective input circuits, to select an input circuit for information unit transmission to that output circuit in a current transmission cycle and to provide hint data indicating a provisional selection, by that output circuit, of an input circuit at a next transmission cycle.

Abstract: A read-ahead mechanism is provided for a redirected Bulk-In endpoint of a USB device. When a USB device is redirected to a server, an agent running on the server can evaluate the USB device's descriptors to determine whether it has any Bulk-In endpoints and whether any Bulk-In endpoint is part of a mass storage interface. For any Bulk-In endpoint that is not part of a mass storage interface, the agent can create a circular buffer and commence originating bulk read requests on the server and then redirecting the bulk read requests to a client-side proxy for delivery to the Bulk-In endpoint. The agent can then store the data it obtains from these bulk read requests in the circular buffer. By repeatedly sending the bulk read requests to the Bulk-In endpoint, the agent ensures that data will be read from the Bulk-In endpoint in a timely manner.

Abstract: A method, system, and computer program product are described for a machine selecting a selected adapter among two or more adapters that perform a same function. The method includes generating a request, at the machine, for the function, and calculating a time indicator associated with each of the two or more adapters based on a respective adapter queue time factor (QTF) associated with each of the two or more adapters, the adapter QTF associated with each of the two or more adapters being a computed value. The method also includes selecting the selected adapter and submitting one or more requests to the selected adapter of the two or more adapters to perform the function based on a comparison of the time indicator associated with each of the two or more adapters.

Abstract: A method, system, and computer program product are described for a machine selecting a selected adapter among two or more adapters that perform a same function. The method includes generating a request, at the machine, for the function, and calculating a time indicator associated with each of the two or more adapters based on a respective adapter queue time factor (QTF) associated with each of the two or more adapters, the adapter QTF associated with each of the two or more adapters being a computed value. The method also includes selecting the selected adapter and submitting one or more requests to the selected adapter of the two or more adapters to perform the function based on a comparison of the time indicator associated with each of the two or more adapters.

Abstract: A rack-mounted system includes a chassis, a switchless board disposed in the chassis, a midplane, and a plurality of device ports. The switchless board includes a baseboard management controller (BMC), a network repeater configured to transport network signals, and a PCIe switch configured to transport PCIe signals. Each of the plurality of device ports is configured to connect a storage device to the midplane and carry the network signals and the PCIe signals over the midplane. The storage device is configurable to operate in one of multiple storage protocol modes based on a type of the chassis. The network repeater of the switchless board is swappable with an Ethernet switch to provide a switching compatibility to the chassis using the same midplane. The storage device can operate in single-port and dual-port configurations.

Abstract: An example computer-implemented method may include receiving, by a general purpose processor, the I/O operation. The method may further include transmitting, by the general purpose processor, the I/O operation to a system assist processor. The method may further include transmitting, by the system assist processor, the I/O operation to an I/O channel for execution by the I/O channel, wherein transmitting the I/O operation to the I/O channel comprises queuing the I/O operation in the multi-queue. The method may further include executing, by the I/O channel, the I/O operation.

Abstract: A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

Abstract: A device may include a connector to connect the device to a chassis. The device may include chassis type circuitry to determine a type of the chassis. The device may further include mode configuration circuitry to configure the device to use a particular mode appropriate for the type of the chassis.

Abstract: A bus node is capable of performing a method, for the assigning of bus node addresses to bus nodes of a serial data bus. The method is performed with the aid of bus shunt resistors in the individual bus nodes of the data bus system in an assignment time period. After the assigning of bus node addresses to the bus nodes in the assignment time period, there follows an operating time period. For this purpose, the bus node comprises such a bus shunt resistor. The bus node is characterized by a bus shunt bypass switch which, prior to assigning a bus node address to the bus node in the assignment time period is opened and which after the assignment of bus node address to the bus node in the assignment time period is closed, and which is closed in the operating time period.