Patents Examined by John A Bodnar
  • Patent number: 11984493
    Abstract: A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of epitaxial source/drain regions connected to the plurality of channel layers. The plurality of channel layers are connected to the plurality of epitaxial source/drain regions via a plurality of epitaxial extension regions. Respective pairs of adjacent channel layers of the plurality of channel layers are connected to a given one of the plurality of epitaxial source/drain regions via respective ones of the plurality of epitaxial extension regions.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: May 14, 2024
    Assignee: International Business Machines Corporation
    Inventors: Nicolas Loubet, Shogo Mochizuki, Kirsten Emilie Moselund, Cezar Bogdan Zota
  • Patent number: 11984490
    Abstract: A semiconductor device includes a first well region in a substrate; a first dielectric layer over the first well region, wherein the first dielectric layer includes a stepped shape over the first well region; and a conductive layer over the first well region. The conductive layer forms a Schottky barrier interface with the first well region.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Han Lin, Te-An Chen
  • Patent number: 11984362
    Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: May 14, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Abbas Ali, Christopher Scott Whitesell, John Christopher Shriner, Henry Litzmann Edwards
  • Patent number: 11984261
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • Patent number: 11985870
    Abstract: A nick is disposed in a display region so as to partly cut the display region. A first routed wire is routed from the display region toward the nick. The first routed wire is included in a first metal layer. A first conductive film is included in a second metal layer. The first routed wire and the first conductive film overlap each other via an inorganic insulating film.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 14, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Makoto Yokoyama, Junichi Yamada
  • Patent number: 11985824
    Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. In one example, a 3D memory device includes a substrate and a memory stack including interleaved conductive layers and dielectric layers on the substrate. The memory stack includes a core structure and a staircase structure. The staircase structure is on one side of the memory stack. The 3D memory device also includes a dummy channel structure extending vertically through the staircase structure. The dummy channel structure includes a plurality of sections along a vertical side of the dummy channel structure. The plurality of sections respectively interface with the interleaved conductive layers in the staircase structure. At least one of the plurality of sections includes a non-flat surface at an interface between the at least one of the plurality of sections and a corresponding conductive layer.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: May 14, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Jianzhong Wu, Jingjing Geng
  • Patent number: 11972984
    Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.
    Type: Grant
    Filed: December 26, 2022
    Date of Patent: April 30, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Wen-An Liang, Chen-Ming Huang
  • Patent number: 11974454
    Abstract: A display device is provided with a first adhesive layer formed on a sealing layer in a display region and a flexible sheet formed on a resin layer on an opposite side of a TFT layer, in which a first inorganic insulating layer has a first slit, the flexible sheet has a second slit, and the first adhesive layer is formed in a state of extending from the display region to a frame region, and overlapping with the first slit and the second slit.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: April 30, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hiroki Kawamura, Keiji Aota, Motoji Shiota
  • Patent number: 11948968
    Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a capacitor contact over a semiconductor substrate, and forming a base layer over the capacitor contact. The method also includes forming a dielectric layer over the base layer, and performing a first doping process to form a first doped region in the dielectric layer. The method further includes etching the dielectric layer such that a sidewall of the dielectric layer is aligned with a sidewall of the first doped region, and removing the first doped region to form a first gap structure in the dielectric layer after the dielectric layer is etched. In addition, the method includes forming a surrounding portion along sidewalls of the dielectric layer and a first interconnect portion in the first gap structure by a deposition process.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: April 2, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hung-Chi Tsai
  • Patent number: 11949022
    Abstract: A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: April 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Zhenyu Lu, Hongbin Zhu, Gordon A. Haller, Roger W. Lindsay, Andrew Bicksler, Brian J. Cleereman, Minsoo Lee
  • Patent number: 11935743
    Abstract: A process for producing a monocrystalline layer of diamond or iridium material comprises transferring a monocrystalline seed layer of SrTiO3 material onto a carrier substrate of silicon material, followed by epitaxial growth of the monocrystalline layer of diamond or iridium material.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: March 19, 2024
    Assignee: SOITEC
    Inventor: Bruno Ghyselen
  • Patent number: 11935920
    Abstract: In an embodiment, a device includes: a first source/drain region; a second source/drain region; an inter-layer dielectric (ILD) layer over the first source/drain region and the second source/drain region; a first source/drain contact extending through the ILD layer, the first source/drain contact connected to the first source/drain region; a second source/drain contact extending through the ILD layer, the second source/drain contact connected to the second source/drain region; and an isolation feature between the first source/drain contact and the second source/drain contact, the isolation feature including a dielectric liner and a void, the dielectric liner surrounding the void.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
  • Patent number: 11935921
    Abstract: A semiconductor device includes a substrate and a semiconductor structure over the substrate. The semiconductor device also includes a first dielectric structure over the substrate, and the first dielectric structure has a first height. The semiconductor device further includes a second dielectric structure over the substrate, and the second dielectric structure has a second height. The second height is smaller than the first height. In addition, the semiconductor device includes a first gate stack wrapped around the first dielectric structure, and the semiconductor structure and the second dielectric structure are spaced apart from the first gate stack. The semiconductor device includes a second gate stack wrapped around the second dielectric structure and the semiconductor structure, and the second gate stack is electrically isolated from the first gate stack.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11929392
    Abstract: Semiconductor devices including a capacitor and methods of forming the same are provided. The semiconductor devices may include a capacitor that include a lower electrode, an upper electrode on the lower electrode, and a dielectric layer extending between the lower electrode and the upper electrode. The lower electrode may include a doped region that contacts the dielectric layer, and the doped region of the lower electrode is configured to increase a capacitance of the capacitor.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: March 12, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gihee Cho, Jungoo Kang, Sangyeol Kang, Hyunsuk Lee
  • Patent number: 11923192
    Abstract: A method for depositing an oxide film on a substrate by a cyclical deposition is disclosed. The method may include: depositing a metal oxide film over the substrate utilizing at least one deposition cycle of a first sub-cycle of the cyclical deposition process; and depositing a silicon oxide film directly on the metal oxide film utilizing at least one deposition cycle of a second sub-cycle of the cyclical deposition process. Semiconductor device structures including an oxide film deposited by the methods of the disclosure are also disclosed.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: March 5, 2024
    Assignee: ASM IP Holding B.V.
    Inventors: Fu Tang, Delphine Longrie, Peng-Fu Hsu
  • Patent number: 11915983
    Abstract: A method of fabricating an electronic device can include forming a plurality of vertical channels having sidewalls over a substrate, and forming gate dielectric regions over portions of the vertical channels and planar regions adjoining the vertical channels. Gate electrode regions are then formed over portions of the gate dielectric regions. The gate electrode material and the vertical channel region are doped and sized to enable full depletion of charges during operation. Source and body tie regions are formed on the vertical sidewalls by doping with a p-type or n-type dopant. Dielectric regions over the gate electrode regions are formed to electrically isolate the gate electrode regions from the source regions. A metallic layer is formed over the first side of the substrate having the vertical channels. Stress is then induced within the substrate by annealing and/or cooling to separate a semiconductor region of the substrate and the metallic layer from the remaining portion of the substrate.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: February 27, 2024
    Assignee: APPLIED NOVEL DEVICES, INC.
    Inventors: Leo Mathew, Rajesh Rao, Daniel Fine, Vishal Trivedi
  • Patent number: 11903212
    Abstract: According to an embodiment, a semiconductor memory device includes a semiconductor substrate, a control circuit arranged on the semiconductor substrate, and a memory cell array arranged above the control circuit. The memory cell array includes a plurality of three-dimensionally-arranged memory cells, and is controlled by the control circuit. A first nitride layer is arranged between the control circuit and the memory cell array, and a second nitride layer is arranged between the control circuit and the first nitride layer.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: February 13, 2024
    Assignee: Kioxia Corporation
    Inventor: Kyungmin Jang
  • Patent number: 11901240
    Abstract: Provided is a vertical field-effect transistor (VFET) device which includes: a substrate; a plurality of single-fin VFETs including respective 1st fin structures on the substrate; and a plurality of multi-fin VFETs each of which includes a plurality of 2nd fin structures on the substrate, wherein a fin pitch of the 2nd fin structures is smaller than a fin pitch of the 1st fin structures.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: February 13, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeonghyuk Yim, Kang Ill Seo
  • Patent number: 11903272
    Abstract: A display substrate includes a plurality of data lines and a plurality of columns of pixel driving circuits. A column of pixel driving circuits is connected to a corresponding data line, and each pixel driving circuit includes a driving transistor and a first transistor. The driving transistor is a P-type transistor. The first transistor includes: a first active pattern having a first channel region, and a first doped region and a second doped region on two opposite sides of the first channel region; a first gate; and a first insulating block disposed on a side of the first active pattern away from the base and having a first via. The data line is connected to a portion of the first active pattern located in the first doped region through the first via. Sizes of all first vias in the column of pixel driving circuits gradually decrease in a first direction.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: February 13, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Honghao Zhao, Wenjun Liao, Yanting Lu, Taoran Zhang, Da Zhou, Jianbo Wang, Wenjin Huang
  • Patent number: 11901364
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Hung Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang