Abstract: An object of the present invention is to provide a vibration sensor in which the frequency dependence of the output is small. The present invention provides a vibration sensor 1 comprising: a support 2; an organic piezoelectric material 3 deformably disposed in or on the support 2; and an electrode 4 for extracting an electrical signal generated by deformation of the organic piezoelectric material 3, the electrode 4 being formed on the organic piezoelectric material 3, the organic piezoelectric material 3 comprising a copolymer of vinylidene fluoride and one or more monomers copolymerizable with vinylidene fluoride.

Abstract: An integrated circuit device including a first electrode layer including a first metal and having a first thermal expansion coefficient; a dielectric layer on the first electrode layer, the dielectric layer including a second metal oxide including a second metal that is different from the first metal, and having a second thermal expansion coefficient that is less than the first thermal expansion coefficient; and a first stress buffer layer between the first electrode layer and the dielectric layer, the first stress buffer layer including a first metal oxide including the first metal, and being formed due to thermal stress of the first electrode layer and thermal stress of the dielectric layer.

Abstract: A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern located on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns, wherein a sidewall of each of the conductive layers protrudes farther towards the channel structure than a sidewall of the hard mask pattern, and wherein the insulating patterns protrude farther towards the channel structure than the sidewall of each of the conductive layers.

Abstract: An energy storage device comprising a substrate comprising a groove having a first and a second face. A capacitor material in the groove. The first and the second face of the groove having a coat of metal. Wherein the coat of metal on the first face is not in electrical contact with the coat of metal on the second face.

Abstract: Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a capacitor device within a recessed portion of a substrate. The recessed portion has sidewalls and a bottom surface below a top surface of the substrate. The semiconductor structure includes a dielectric material disposed below the capacitor device and within the recessed portion. The semiconductor structure includes a first conductive structure adjacent one or more of the sidewalls of the recessed portion. The first conductive structure may include a conductive portion of the substrate or a conductive material disposed within the recessed portion. The semiconductor structure includes a second conductive structure coupled to the first conductive structure, where the second conductive structure provides an electrical connection from the first conductive structure to a voltage source or a voltage drain.

Abstract: A method of forming a MEMS device includes providing a substrate having a device stopper. The device stopper is integral to the substrate and formed of the substrate material. A thermal dielectric isolation layer may be arranged over the device stopper and the substrate. A device cavity may be formed in the substrate and the thermal dielectric isolation layer. The thermal dielectric isolation layer and the device stopper at least partially surround the device cavity. An active device layer may be formed over the thermal dielectric isolation layer and the device cavity.

Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

Abstract: Provided is a transducer that can be manufactured without using a volatile adhesive or an organic solvent. A transducer is provided with: a first electrode sheet provided with a plurality of first through-holes; a dielectric layer, of which a first surface is disposed on the first-electrode-sheet side; and a first fusion-bonding layer formed from a fusion-bonding material, the first fusion-bonding layer joining together, by fusion bonding of the fusion-bonding material, a boundary region between a body portion of the dielectric layer and a first inner surface of the first electrode sheet and a boundary region between the body portion of the dielectric layer and a first inner circumferential surface of at least some of the plurality of first through-holes.

Abstract: A display apparatus includes a driving substrate and a first light emitting diode element. The driving substrate has a plurality of driving structures. Each of the driving structures includes a first pad, a second pad, a third pad and a fourth pad. The plurality of driving structures include a first driving structure. The first light emitting diode element is electrically connected to a first pad and a second pad of the first driving structure, and the first light emitting diode element crosses a line connecting a third pad and a fourth pad of the first driving structure. A manufacturing method of the display apparatus is also provided.

Abstract: In a general aspect, a semiconductor device can include a semiconductor region, an active region disposed in the semiconductor region, a termination region disposed on the semiconductor region and adjacent to the active region, and a resistor disposed in the termination region. The resistor can include a trench, a conductive material disposed in the trench, and a first cavity separating the trench from the semiconductor region. A portion of the first cavity can be disposed between a bottom of the trench and the semiconductor region. The resistor can further include a second cavity separating the trench from the semiconductor region.

Abstract: Disclosed herein are quantum dot devices with trenched substrates, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate having a trench disposed therein, wherein a bottom of the trench is provided by a first material, and a quantum well stack at least partially disposed in the trench. A material of the quantum well stack may be in contact with the bottom of the trench, and the material of the quantum well stack may be different from the first material.

Abstract: A semiconductor device includes a plurality of first stack structures formed in a first area of a substrate, wherein the plurality of first stack structures are configured to form a plurality of first transistors that operate under a first voltage level. The semiconductor device includes a plurality of second stack structures formed in a second area of the substrate, wherein the plurality of second stack structures are configured to form a plurality of second transistors that operate under a second voltage level greater than the first voltage level. The semiconductor device includes a first isolation structure disposed between neighboring ones of the plurality of first stack structures and has a first height. The semiconductor device includes a second isolation structure disposed between neighboring ones of the plurality of second stack structures and has a second height. The first height is greater than the second height.

Abstract: A method for fabricating memory device includes: providing a substrate having a bottom electrode layer therein, forming a buffer layer and a mask layer on the buffer layer over the substrate, in contact with the bottom electrode layer, performing an advanced oxidation process on a sidewall of the buffer layer to form a resistive layer, which surrounds the whole sidewall of the buffer layer and extends upward vertically from the substrate, and forming, over the substrate, a noble metal layer and a top electrode layer on the noble metal layer, fully covering the resistive layer and the mask layer.

Abstract: A method for forming non-planar capacitors of desired dimensions is disclosed. The method is based on providing a three-dimensional structure of a first material over a substrate, enclosing the structure with a second material that is sufficiently etch-selective with respect to the first material, and then performing a wet etch to remove most of the first material but not the second material, thus forming a cavity within the second material. Shape and dimensions of the cavity are comparable to those desired for the final non-planar capacitor. At least one electrode of a capacitor may then be formed within the cavity. Using the etch selectivity of the first and second materials advantageously allows applying wet etch techniques for forming high aspect ratio openings in fabricating non-planar capacitors, which is easier and more reliable than relying on dry etch techniques.

Abstract: A first gate and a second gate are formed on a substrate with a gap between the first and second gates. The first gate has a first sidewall. The second gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.

Abstract: The present invention is directed to a method for manufacturing an ultrasonic fingerprint sensor by using a nanorod structure, the method including: a conductive mold generating step of generating a plurality of rod generation holes; a nanorod generating step of generating nanorods by filling the plurality of rod generation holes with a nano-piezoelectric material; a side electrode generation portion marking step of marking side electrode generation portions; a conductive mold etching step of generating nanorods and side electrodes by performing primary etching on the conductive mold; an insulating material filling step of filling portions with an insulating material; a lower electrode forming step of performing secondary etching and forming lower electrodes; a dummy substrate bonding step of bonding a dummy substrate to a surface on which the lower electrodes are formed; and an upper electrode forming step of removing the conductive substrate base and forming upper electrodes.

Abstract: An energy storage device comprising a substrate comprising a series of grooves. Each groove having a first and a second face. Wherein there is a capacitor material in each groove of the series of grooves.

Abstract: A compact vertical semiconductor device and a manufacturing method thereof, and an electronic apparatus including the semiconductor device are provided, and the vertical semiconductor device may include: a plurality of vertical unit devices stacked on each other, in which the unit devices include respective gate stacks extending in a lateral direction, and each of the gate stacks includes a main body, an end portion, and a connection portion located between the main body and the end portion, and in a top view, a periphery of the connection portion is recessed relative to peripheries of the main body and the end portion; and a contact portion located on the end portion of each of the gate stacks, in which the contact portion is in contact with the end portion.

Abstract: Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.