Abstract: In a data processing device which consists of a plurality of parallel-operating modules, each of the four modules is provided with its own clock circuit. Synchronization is realized at the level of the cycle of the high frequency oscillation. This is realized in that each of the clock circuits includes a two-out-of-three majority decision device which is fed by the output clock signals of the other three clock circuits. The majority decision may have a simple logic structure and is connected to the actual clock function generator in order to reduce, using a readjustment circuit, the deviation between the clock function signal and the majority signal by a factor substantially smaller than one for each transition of the majority signal.

Abstract: An adaptive processor array is capable of learning certain flexible or variable associations which learned associations are useful in recognizing classes of inputs, i.e., capable of associating certain types of inputs to fall in the same output basin or field. The adaptive processor array comprises a plurality of identical processing cells arranged in parallel columns and rows to form a two dimensional matrix. Each of the cells in the array include logic and a memory for storing an internal state. The first row of cells in the array form a parallel input to the array and the last row of cells in the array form a parallel output from the array.

Abstract: A two-pass method for relocating a set of linked control blocks stored away on a persistent medium after a first pass and then rewritten into internal memory of a computing facility during second and subsequent passes each time an application to which the control blocks are bound is executed. The first pass involves path following and coloring pointers affected by the relocation, mapping discontiguously located blocks into a linear address space, changing affected control blocks to location offsets, and writing out the linked control blocks to DASD store. Upon the second pass, virtual addresses are substituted for the offsets upon rewriting of the control blocks to internal memory.

Abstract: A data processing system for array computation including a global memory, a control processor unit for executing microprograms preloaded from the global memory in a local memory of the processor unit, and an array processor unit controlled by the instructions generated by the control processor unit from the microprograms for executing array computations with an array of data preloaded from the global memory into a local array memory, the selected architecture of the array processor unit being dynamically reconfigurable to best meet array computation to be performed, and to provide reduced overhead operations.

Abstract: A parallel processing system is receptive of a program and has at least two processors connected in parallel to a shared main memory. Each processor executes instructions of the program which includes side-effecting instructions which modify the contents of a location in main memory and functional instructions which reference locations in main memory. The program is compiled into a series of independent instruction blocks each of which includes predominantly functional instructions and terminates in a side-effecting instruction and the processors execute the blocks in parallel.

Abstract: A is a duel processor system (100) with duplicated memory (114,124) has two modes (10,11) of operation: a converged mode (10) in which one of the two processors (101,102) is active and executing all system tasks while the other processor is inactive; and a diverged mode (11) in which both processors are active and independently executing different tasks. The system automatically changes modes in response to requests such as manual and program control and certain system fault conditions. In diverged mode, the system may be in either of two states of operation (1 and 2). In one state (1) one processor (101) is designated a primary processor, and in the other state (2) the other processor (102) is designated the primary processor. In the converged mode the system may be in either of four states of operaton (3-6). In two of these states (3,4) one processor is active while the other processor is standing by ready to take up execution of tasks from the point where the one processor stoped execution.

Abstract: A high speed buffer store arrangement for use in a data processing system having multiple cache buffer storage units in a hierarchial arrangement permits fast transfer of wide data blocks. On each cache chip, input and output latches are integrated thus avoiding separate intermediate buffering. Input and output latches are interconnected by 64-byte wide data buses so that data blocks can be shifted rapidly from one cache hierarchy level to another and back. Chip-internal feedback connections from output to input latches allow data blocks to be selectively reentered into a cache after reading. An additional register array is provided so that data blocks can be furnished again after transfer from cache to main memory or CPU without accessing the respective cache. Wide data blocks can be transferred within one cycle, thus tying up caches much less in transfer operations, so that they have increased availability.

Abstract: The method and means of fault-tolerant processing includes a plurality of system building blocks, each including a real-time processor and specialized processors and local non-volatile memory that are coupled to communicate internally within each of the system building blocks, which, in turn, communicate with one another over local-area network links, and communicate with the remainder of the system over an I/O bus controlled by an I/O processor. Transaction-based processing is under control of a transaction coordinator which permits all of the transaction operations to complete successfully and then alter stored data for the completed transaction, or not to alter any stored data if a transaction is not completed. The transaction coordinator maintains a record of the distributed file accesses required during processing of a transaction, and prevents other transactions from altering stored data during processing of a transaction.

Abstract: A slave-type interface circuit which can receive signals from a bus if the coding A.sub.0, A.sub.1 and A.sub.2 of its inputs S.sub.0, S.sub.1 and S.sub.2 corresponds to that mode of operation. The signals from the bus are then delivered to the inputs L.sub.1 and L.sub.2. With another mode of operation the coding of inputs S.sub.0, S.sub.1 and S.sub.2 corresponds to off-line operation on the basis of logic levels applied to the same inputs L.sub.1 and L.sub.2. A branching block (SBL) directs the signals from the inputs L.sub.1 and L.sub.2 either to a bus receiver RBUS or directly to a decoder CDEC controlling a group of switches (COM). In the case of operation with a bus, the bus receiver (RBUS) controls the logic for the progress for operations.

Abstract: In a virtual machine system having a bare machine including an execution control unit, a storage control unit and a main storage unit and having a hardware architecture of its own, for supporting at least one virtual machine which runs on the bare machine and has a different hardware architecture than the bare machine, microinstructions for executing the instructions of the virtual machine are stored in storage means, and, in dispatching, the microinstructions in the microprogram associated with the virtual machine selected to be run on the bare machine are sequentially fetched from the storage means and executed by the execution control unit.

Abstract: A multinode parallel-processing computer is made up of a plurality of innerconnected, large capacity nodes each including a reconfigurable pipeline of functional units such as Integer Arithmetic Logic Processors, Floating Point Arithmetic Processors, Special Purpose Processors, etc. The reconfigurable pipeline of each node is connected to a multiplane memory by a Memory-ALU switch NETwork (MASNET). The reconfigurable pipeline includes three (3) basic substructures formed from functional units which have been found to be sufficient to perform the bulk of all calculations. The MASNET controls the flow of signals from the memory planes to the reconfigurable pipeline and vice versa. the nodes are connectable together by an internode data router (hyperspace router) so as to form a hypercube configuration. The capability of the nodes to conditionally configure the pipeline at each tick of the clock, without requiring a pipeline flush, permits many powerful algorithms to be implemented directly.

Abstract: A plurality of data bands operable independently from each other is controlled by a control circuit so that a set of received data signals are written into respective storage locations predetermined for respective data signals within respective data banks predetermined for respective data signals, wherein respective storage locations and respective data banks for respective received data signals are predetermined depending upon the arrival numbers of respective received data signals and a predetermined bank order, so that respective storage locations for two data signals received one after another belong to different data banks arranged according to the bank order. The data banks are controlled by the control circuit so that a set of data signals are read out according to the order of receipt of the set of data signals and from a timing before completion of the writing of the set under a condition that each data bank performs only one of write and read operations during a clock period.

Abstract: A microprogrammed parallel processor including a plurality of subprocessors operates under the control of microinstructions. Each microinstruction contains a plurality of micro-operations each of which requires one or more subprocessors for execution. All micro-operations for which required subprocessors are available are immediately carried out. Any remaining micro-operations within a microinstruction which are not executed due to lack of subprocessor availability are recycled. These remaining micro-operations are executed in subsequent cycles as a required subprocessor becomes available. The entire microinstruction is not recycled but only those portions of it, i.e., the unexecuted micro-operations, are recycled and executed in a subsequent cycle. The microinstruction being executed is stored in a latch until all micro-operations within the microinstruction are executed. At that time, the next microinstruction is fetched into the latch.

Abstract: A data processing device for processing a data sequence obtained by sampling an information signal, is arranged to compute a plurality of data before and/or after an incorrect data amoung the data sequence, to have data obtained by rounding up or rounding off the results of computation at about the same rate, and to replace the incorrect data with the computed data.

Abstract: This invention is so arranged that, in a dynamic random access memory including a display memory area storing therein the display data and a system memory area employed for arithmetic operation in a central processing unit, memory refresh is accomplished by a display address signal applied to the dynamic random access memory when information stored in the dynamic random access memory is utilized for display, and a refresh address signal from a refresh counter for generating such a refresh address signal is applied to the random access memory as a burst signal for a predetermined period at predetermined intervals during a display frame time, thus refreshing memory, when information stored in the dynamic random access memory is not utilized for display.

Abstract: A method for detecting and handling memory-mapped I/O in a pipelined data processing system is provided. The method uses two signals on the system interface: when the system generates a read bus cycle, it activates an output signal if certain I/O requirements are not satisfied; an input signal is activated when the reference is to a peripheral device that exhibits certain characteristics; when the system detects that both the input signal and the output signal are active, it discards the data read during the bus cycle, serializes instruction execution and regenerates the read bus cycle, this time satisfying the requirements for I/O such that the output signal is driven inactive.

Abstract: A system is disclosed for determining the authenticity of computer software when used with a main processor unit. The software is stored in an external memory which may, for example, be in the form of a ROM cartridge, floppy disk or the like. The main processor unit is operated according to a program contained in the external memory. To verify that the external memory is authentic, duplicate semiconductor devices, for example microprocessors, are separately mounted with the external memory and in the main unit, respectively. The semiconductor associated with the external memory device acts as a key device and the duplicate device mounted in the main unit acts as a lock device. The key device and the lock device are synchronized with each other, executing the same arithmetic operation according to the same program. The results of these operations are exchanged between devices, and compared.

Abstract: In processor arrays for image processors it is useful to be able to determine which is the "top left" array element having a value above or below a threshold. In the present invention an array of processors includes a number of priority encoder circuits connected to the processors to give the address of the top left array element which has a predetermined significance. Decoder circuits are provided to allow particular processors to be addressed, and methods of counting the number of array elements having a predetermined significance, and of reading data to and from the processors, are also described.

Abstract: A hybrid associative memory has a non-associative basic storage and an associative surface. Every data unit individually selectable in the basic storage is sub-divided into sub-units, and a logic unit ALV of corresponding working capacity is provided in the associative surface for every sub-unit. In order for either the sub-units of a data unit or the respectively corresponding sub-units of a corresponding plurality of data units to be connected through to the associative surface as a data unit, the storage of the data units in the basic storage is divided into areas. Every area is formed of a plurality of data units corresponding in number to the plurality of sub-units of the data unit. The sub-units of all data units of an area are ordered in offset fashion therein in accordance with a prescribed classification pattern. The access to a data unit is internally controlled via an address re-ordering unit for the row address in the address controller.

Abstract: A direct memory access device has an increment counter for indicating an address increment between succeeding transfer blocks of data from a first storage location to a second storage location within a memory device. Each block of data has a lateral width determined by the content of a line byte counter associated with both the source and destination areas of the memory device. After the transfer of each block of data, the address is advanced by an amount corresponding to the content of the increment counter. The direct memory access device is capable of multi-dimensional data transfers; for example, two- and three-dimensional transfers.