Abstract: A system for interfacing a Processor to a Coprocessor using standard bus cycles. The processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires the Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

Abstract: A tunable operating system in a multiprogrammed data processing system prevents lockout of I/O bound tasks of low priority by CPU bound tasks of high priority. A range signal in the master control block and a range divider signal in each task control block together define a queue subset for each task. The queue subsets for different tasks are overlapped by at least one queue, and preferably by at least three queues. A plurality of time-slice values, preferably two, are assigned when tasks are dispatched; the time-slice values are assigned with respect to the task range divider signal and therefore are not fixed with respect to each queue. The invention permits the weight given to the user-set task priority and to the priority based on recent task behavior to be varied as desired. The range value, the divider values, and the time-slice values are variable to permit tuning of the operating system.

Abstract: A data processing system having a plurality of FIFO memories and a plurality of ALUs and in which a FIFO memory may be selected to receive a set of data signals from an ALU and at the same time to be selected to provide a set of data signals to another ALU, with the result that the selected FIFO memory performs read and write operations concurrently and intermittently. Also, a set of data signals held by one of the FIFO memories may be transferred to a selected ALU for effecting a logical or arithmetic operation thereon, and the data signals representing the result of the logical or arithmetic operation thereon, and the data signals representing the result of the logical or arithmetic operation by the selected ALU may be transferred to another FIFO memory.

Abstract: A method of access validation whereby a false system becomes bound to an accessing user if an unacceptable accessing pattern is detected. The false system interacts in a mode similar to the conversational protocols of target systems but remains logically insulated from said target systems. Concurrent messages to security monitors at binding time ensure entrapment.

Abstract: An information processing system having a high speed buffer storage and employing an advanced control includes an address stack for storing addresses to be sent to a main storage as readout requests when instruction words or data are not contained in the high speed buffer storage, together with instruction stream numbers and flags for indicating whether the readout requests are conditional requests based on predicted prefetching. For the addresses having the conditional request flags, they are sent as the readout requests when the prediction is finally determined and the other addresses are cancelled. In this manner, the advanced control need not be interrupted.

Abstract: A multiprocessor system used, for example, in a personal computer, wherein different types of microprocessors are used independently of the architecture of each microprocessor. The system includes a control register, a control circuit, and a common peripheral circuit mounted, for example, on a main board, and a plurality of kinds of microprocessors each mounted, for example, on a sub-board connected to the main board. The control circuit transmits a halt request signal to a first microprocessor which is currently operating, in response to coincidence between an output signal of the control register and the status signal indicating that a second microprocessor is in a halt condition, when the output signal of the control register is changed by the first microprocessor.

Abstract: A device for making a 16-bit data bus microprocessor compatible with peripherals, expansion devices and associated software designed for an 8-bit data bus. The 16-bit data bus is divided into high and low portions, the low portion of which is coupled to the 8-bit data bus by a buffer which is disabled or enabled. The high portion is selectively coupled to the 8-bit data bus when a high data byte is to be transferred either during 8-bit byte operation or in word operations. The device may be bypassed when 16-bit data bus expansion devices or peripherals are used.

Abstract: An integrated circuit microcomputer with EEPROM has a limited number of modes for operation. In at least first and second modes, the inner workings of the microcomputer, including the contents of the EEPROM, can be read externally from the microcomputer. An EEPROM security bit, when set, prevents the first mode from being entered and causes the EEPROM to be erased when the second mode is entered. The EEPROM is also erased if the security bit is erased.

Abstract: A general bit manipulator structure for parallel accessing a variable width data bus wherein, with a data bus of variable width N.sub.c and a data field of N.sub.f, the structure can place the data field on the data bus with bit 1 of the data field aligned with a selected bit n within the data bus width. If the data field N.sub.f extends beyond the end of the data bus, the overflow bits of the data field are "wrapped around" and placed at the beginning of the data bus starting at position 1 of the data bus. Also, special signals are generated and accompany these overflow or wrapped bits. Furthermore, select signals are generated to indicate which bits of the data bus contain valid data when the width of the data field is less than the width of the data bus. The structure includes a modulo N.sub.c combinational ring shifter for aligning the data field with the data bus.

Abstract: A data processing system includes a cathode ray tube (CRT) display subsystem and a floppy disk subsystem. The logic of both systems are verified by generating and transferring a fixed format stream of data bits from the CRT display subsystem to the floppy disk subsystem in modified frequency modulation (MFM) mode and checking the information received by the floppy disk subsystem against the original information presented to the CRT display subsystem.

Abstract: Apparatus and method for decoding computer operation codes. The operation code is decoded into a single product term in the AND array of a programmable logic array. That single product term is then processed through a clock driven sequencer to generate a plurality of sequential product terms. These sequential product terms are decoded by the OR array of the programmable logic array to generate a plurality of sequential time states comprising the decoded operation code.

Abstract: A plurality of switching modules, e.g. components of a digital telephone exchange, each include a pair of central processing units (CPUs) operating in master-slave relationship under the supervisory control of two support processors alos constituting a master-slave pair. Each support processor communicates via a respective bus with all switching modules by way of respective signal lines extending from that bus to one CPU of each pair. Each signal line includes two closely juxtaposed, cascaded interfaces each of which, in turn, has an externally and an internally accessible input/output (I/O) section. The externally accessible I/O section of each interface inserted in the active line between the master processor and the master CPU of any module is normally operational and communicates by an in-line link with the corresponding I/O section of the interface in cascade therewith.

Abstract: Three hardware real time clock subcircuits are connected in a triple modular redundancy configuration to assure continued operation if one subcircuit fails. A power supply or processor failure will not cause a clock supplying other processors to fail. Output of voted master clock pulses to the counter in every subcircuit is inhibited until all power supplies are turned on and stabilized, and the time base of the real time clock pulses is variable. The output pulses of all subcircuits are voted on and the voter output is the real time clock. The master clock can be the processor clock.

Abstract: Recurring data sample values of a common parameter are stored in nonvolatile memory at different addresses so as to limit the maximum number of entries at any one location to less than that which results in loss of storage ability.

Abstract: According to a shift circuit of the present invention, two single-word length data shifters of 2.sup.n bits are arranged in parallel. Further, a selective output section is provided to selectively supply the upper 2.sup.n bits or the lower 2.sup.n bits of the double-word length data of 2.sup.n+1 bits, sign of the data and constant to an individual section in accordance with the number of the shift and the type of shift such as the shift direction, arithmetic shift or logical shift. One shifter produces the upper 2.sup.n bits of the shifted data as a result of the shift operation of the double-word length data of 2.sup.n+1 bits, and the other shifter produces the lower 2.sup.n bits thereof while the two shifters operate independently in accordance with the same contents of a shifting number register.

Abstract: An electronic cash register inhibits registration of information associated with a commodity unless an operator code comprised of a plurality of digits and identifying an operator is inputted. A preset code further allows selection of the manner of indicating and printing the inputted operator code. When an operator code comprised of a plurality of digits is entered by operating a decimal keyboard or ten-key (1) and an operator code key and when a first mode is set through a mode selection key (7), all the digits of the operator code are displayed in a display (11) and printed in a printer (12). If and when a second mode is set, only a predetermined partial digit or digits of the operator code comprised of a plurality of digits are printed and none of digits are displayed. If a third mode is set, both displaying and printing of the operator code are inhibited. Thus, a user can arbitrarily select whether the operator code should be displayed and printed, by switching the mode.

Abstract: An improved apparatus for forming an ordered sequence of n digital numbers from a randomly arranged set of n digital numbers is shown to be made up of: (a) n registers, each initially holding a different one of the randomly arranged set of n digital numbers; (b) a digital comparator for each adjacent pair of registers to determine whether or not the digital numbers in each adjacent pair of registers are in the ordered sequence and to interchange the digital numbers in any adjacent pair of registers whenever such numbers are not in the ordered sequence; and (c) a switching arrangement, operative in response to each successive one of (2n-1) clock pulses, alternately to switch each digital comparator from the associated adjacent pair of registers to a different selected pair of registers whereby the digital numbers may be shifted through the n registers as required to form the ordered sequence.

Abstract: A technique of determining the distribution of pulses along two perpendicular X-Y axes of a numerically controlled machine can be used for linear, circular, and parabolic interpolations and may be extended to computer graphics. At the initial point on the curve and at each succeeding point, a decision is made to increment the X axis, the Y axis, or both axes. This decision is based on a deviation index which is an index of closeness to the desired curve. Hardware is minimized and involves only additions, compares, shifts, and increments/decrements.

Abstract: In a data processing system including a dynamic RAM (14) and a programmable, prioritized direct memory access (DMA) controller (16) having a plurality of channels, the highest priority channel (0) is dedicated to a memory refresh operation. The system clock (P CLK) from the CPU (12) is applied to a divider counter (22) which produces a refresh clock (R CLK) having a period sufficient to generate the minimum number of refresh cycles within the minimum period required to refresh the RAM (14). The refresh clock (R CLK) is used to set a "D-type" latch (24) whose output, in turn, sets the highest priority DMA channel (0) request line (DREQ0), thereby initiating a memory refresh cycle. The latch (24) is cleared by the DMA acknowledge signal (DACK0) indicating the cycle is completed.