Abstract: A method of emulating the instructions of a target computer in the instructions of a host computer to operate the host computer in accordance with the target computer instructions, the target computer having the capability of modifying its own instructions and data during operation, includes the steps of storing the target instructions in a target memory segment, sequentially withdrawing the target instructions from the target memory segment and executing the target instructions in the host computer, constructing a template of the host instructions for each of the target instructions executed, storing each of the templates for reuse each time the corresponding target instruction is to be executed, limiting access to those target instructions in the target memory segment which have been stored in one of the templates to permit only read operations to be performed thereon, and detectng a target instruction which attempts a write operation on one of the target instructions which is in a stored template.

Abstract: In a centrally controlled resource arbitration system, each of the units concurrently requesting access sends its identity code and the binary complement thereof to a central arbitration processor. The identity codes are logically combined into a first word, and the binary complements are logically combined into a second word. A subset identifier of the requesting units is then formed by combining corresponding bits of the first and second words. Unresolved values in the subset identifier are iteratively removed to eliminate a subset of the requesting units. When all but one of the requesting units have been eliminated, access to the resource is given to the remaining unit.

Abstract: A display system for displaying select dynamic process data of plant operations to an operator providing a display of only dynamic data having a predetermined difference between current and stored values.

Abstract: A priority apportioning arrangement for computers with processors of two types, namely a first high-priority type which can determine its priority itself in relation to processors of a second low-priority type when using a common bus. The arrangement contains a first logic circuit (20) which has its first input activated on a request for access from one of the low-priority units (3a-3h), its second input activated on a request for access from the high-priority unit (1) and its third activated during the whole time the bus is used and has two outputs for assigning the bus a low-priority unit or the high-priority unit.

Abstract: The control unit is arranged to handle the requests for transmission and reception interrupts (i.e. requests to the central logic unit CPU to halt its operative program in order to transmit or receive messages to or from a peripheral unit) in arrival from the input/output interface circuits, each of which is associated with a peripheral unit. To this purpose, the interface circuits are cyclically scanned to groups of n: the presence of at least one interrupt request halts the scanning and causes a request criterion to be transmitted to the central logic unit (CPU) by the control unit. The address of the peripheral unit presenting the highest priority among those of the group requiring an interrupt is written into the state register of the control unit, the address being composed of the number of the group (supplied by the scanner) and by the code generated by a priority coder.

Abstract: Apparatus is disclosed for selecting a group of address signals to be applied to a memory unit array and for applying the address signals to the memory unit array to permit the activity associated with the address signals to be completed. The apparatus generates a multiplicity of signals controlling a latch-type buffer storage unit. The first generated signal insures that the signal controlling the buffer storage unit is active during application of the address signals to the system bus. The second generated signal overlaps the first generated signal and extends the signal controlling the buffer storage unit a small amount. The third generated signal overlaps the second generated signal and extends the signal controlling the buffer storage unit for the period of time necessary to utilize the memory unit array.

Abstract: A delay circuit for a data manipulation circuit is provided in which data update signals to the data manipulation circuit are delayed when a data access signal is present so that data is not manipulated during accessing of the data.

Abstract: Devices for interconnection into a digital computer system contain arbitration mechanisms for assigning control of a common communications path among the devices. Several modes of device arbitration are provided for, and the modes may be mixed among devices, and changed during operation of the system, in the system without interfering with communications. The arbitration mechanism requires only a single additional line in the communications pathway, and thus a single additional pin on the integrated circuit on which it is implemented, for the arbitration function. It thus facilitates implementation of the arbitration mechanism along with all other interconnect logic on a single integrated circuit.

Abstract: A program access system that enables calling programs included in a first load module to CALL a callable program included within a second load module. The method of the present invention includes the steps of loading and commencing execution of the first load module, and upon the occurrence of a CALL from a calling program to the callable program, executing different steps depending on whether or not the callable program has already been loaded. When the callable program has not yet been loaded, the method includes the steps of determining the name of the second load module in which the callable program is included, loading the second load module, determining the actual address of the callable program, storing the actual address, and transferring control to the callable program at the actual address.

Abstract: A computer system including a processor and memory, the processor having a virtual mode of operation in which it uses a virtual machine monitor which allows it to service a plurality of users contemporaneously in a multiplexed manner, and a non-virtual, or real, mode of operation. The computer system has a set of at least three operation mode protection rings representing a hierarchy of access privilege levels in both the real and virtual modes, with the number of privilege levels in both the real and virtual modes being the same. The privilege levels govern the accessibility of memory locations to programs and the executability of certain privileged instructions, which cause control to be transferred to the virtual machine monitor when the processor is in a virtual mode.

Abstract: A one-chip, integrated-circuit, 32-bit bipolar arithmetic-logic unit (ALU) capable of performing complex operations on selected one, two, three, or four 8-bit bytes or selected contiguous bits of the operands in a single clock cycle. The ALU has three 32-bit inputs consisting of two data word operands and a mask; operand with shifters provided at one of the operand input, the mask input and at the ALU output so that three operands can be simultaneously received, shifted, masked, combined, and the result shifted in a single instruction cycle. Bit positions which are not selected to take part in an ALU operation pass unaffected to the outputs from one of the data word inputs. A swap multiplexer is present at the data word inputs to afford interchanging of these inputs before processing by the ALU.

Abstract: Equipping individual processing elements with an instruction adapter provides an array processor with adaptive spatial-dependent and data-dependent processing capability. The instruction becomes variable, at the processing element level, in response to spatial and data parameters of the data stream. An array processor can be optimized, for example, to carry out very different instructions on spatial-dependent data such as blank margin surrounding the black lines of a sketch. Similarly, the array processor can be optimized for data-dependent values, for example to execute different instructions for positive data values than for negative data values. Providing each processing element with a processor identification register permits an easy setup by flowing the setup values to the individual processing elements, together with setup of condition control values.

Abstract: A multiprocessor system includes a priority discriminator which passes a request signal from a master operation processing unit serially through a plurality of slave operation processing units in accordance with a predetermined priority sequence of the slave operation processing units until an idle slave operation processing unit having a processing capability called for by a command signal from the master operation processing unit is found. The priority discriminator interconnecting the slave operation processing unit relieves the master operation processing unit of priority and slave unit selection tasks.

Abstract: An information processing system includes a loop-shaped signal transmission line for transmitting data to be stored, a plurality of transmission control processors disposed around the transmission line, and information processing units for inputting and outputting data to and from the signal transmission line through the corresponding transmission control processors. Each of the transmission control processors is adapted to variably control the signal amplitude of data flowing around the signal transmission line in accordance with the utilization of the data in the corresponding information processing unit.

Abstract: A microprocessor based mailing system, wherein postal rate charts are provided on portable media such as floppy disks, having the capability to update such postal rate charts. The mailing system includes a microcomputer system made up of a microprocessor, a CRT display, a keyboard, dual disk drives and printer; a scale for determining the weight of items to be mailed, and an optional postal meter. The microprocessor determines the appropriate postage for items to be mailed in accordance with the item's weight, postal information input by an operator and postal rate charts stored on a first disk in one of the disk drives. To update the postal rate charts a second disk may be substituted for the first while the first disk is shifted to the other drive. The second disk contains updating information and an updating program to update the rate charts. Upon initialization of the system the updating program is loaded and executed.

Abstract: Disclosed is a slave processor (100) for a multiprocessor logic circuit fault simulator. The slave processor has a hardware-based list processor (110) for performing set algebra operations on fault lists (300). The operation of the list processor centers on a characteristic vector (A) that has a bit (360) for each fault number (310) that can appear in a fault list. The bits are implemented in bit locations (210) of a register (201). The list processor also has a second vector (B), implemented in a register (202), whose bit locations form shift register pairs (208) with locations of vector A bits to store values of vector A bits shifted out by entry of new values. The list processor further has two stacks (A, B), implemented in memories (203, 204), for storing fault numbers. As fault numbers of a first fault list are loaded into the list processor, corresponding vector A bits are set, and the fault numbers are pushed onto the stack A.

Abstract: An apparatus for controlling access to a program stored in a read-only memory is described. In one embodiment, the memory includes a random number generator and an encryptor for encrypting random numbers from the generator. A second encryptor which provides identical encryption to the first encryptor is included within the system and is coupled to receive random numbers from the generator. A comparator compares the results from the first and second encryptors and if they are identical, enables the memory. The encryptors are programmable with a 64-bit key and 32-bit random numbers are used. By making the encryption process relatively slow (e.g., one second) many decades are required to break the key.

Abstract: A virtual stack structure utilizing Write Pointers and Read Pointers for providing pipelined data words on a first-in first-out basis to a memory structure is described. The virtual stack structure incorporates a plurality of Stack Registers each having an unique Write Tag and Read Tag associated therewith. The Write Tags are utilized to through-check the decoding of the Write Pointer and to issue Write Tag Error signals when it is determined that the Write Pointer has been improperly decoded. Circuitry is provided for checking the appropriate loading of the Write Pointer in the stack, and issuing an error signal when improper loading is sensed. Each of the Stack Registers has an unique Read Tag associated therewith that is utilized to through-check the decoding of the Read Pointer and to issue Read Tag Error signals when improper decoding is detected.

Abstract: An interactive terminal system transfers information at 750,000 bits per second between a central system and a number of work stations, all coupled in common to a single conductor coaxial bus. The central system prepolls an addressed work station before sending a block of information. The prepoll conditions the work station to prepare to receive a block of information.

Abstract: A multi-digit, mixed-base or mixed-radix counter of the type used in digital computing devices wherein the value of each digit of the counter is stored in two parts: a first part being the normal numerical value except in certain exceptional cases; and a second part which is zero except in the exceptional cases in which it is a binary one. The exceptional case is when the value to be represented by the counter digit is a terminal digit value, i.e., a maximum digit value when the counter is incrementing or zero value when the counter is decrementing. In the case of a decrementing counter where the normal terminal digit value is a zero, each zero value is replaced with the corresponding maximum digit value for that digit in the first part of the counter, but the second part of the counter identifies in which (if any) of the digits of the first part of the counter such a substitution has been made.