Abstract: A transistor in an embodiment includes an oxide semiconductor layer on a substrate, the oxide semiconductor layer including a first region and a second region, a first gate electrode including a region overlapping the oxide semiconductor layer, the first gate electrode being arranged on a surface of the oxide semiconductor layer opposite to the substrate, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a first oxide conductive layer and a second oxide conductive layer between the oxide semiconductor layer and the substrate, the first oxide conductive layer and the second oxide conductive layer each including a region in contact with the oxide semiconductor layer.

Abstract: A method of manufacturing a display device includes forming a first light-emitting area on a substrate, and forming a first color adjustment pattern on the first light-emitting area by emitting first light from the first light-emitting area, wherein the first light-emitting area includes a first semiconductor layer, a second semiconductor layer provided on the first semiconductor layer, a first active layer arranged between the first semiconductor layer and the second semiconductor layer, a first contact electrically connecting the substrate and the first semiconductor layer, and a first preliminary common electrode electrically connected to the second semiconductor layer.

Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.

Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a metal layer; and a conductive layer positioned between the silicon carbide layer and the metal layer, the conductive layer containing a silicide of one metal element (M) selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), and the conductive layer having a carbon concentration of 1×1017 cm?3 or less.

Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first metal layer on the insulating substrate, a first insulating layer on the insulating substrate and the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer and the first insulating layer, a second metal layer on the second insulating layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer. The first metal layer overlaps the second metal layer. A third metal layer contacts a top surface of the second metal layer and a top surface of the first metal layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor fin over a substrate and multiple semiconductor nanostructures suspended over the semiconductor fin. The semiconductor device structure also includes a gate stack extending across the semiconductor fin, and the gate stack wraps around each of the semiconductor nanostructures. The semiconductor device structure further includes a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. In addition, the semiconductor device structure includes an isolation structure between the semiconductor fin and the gate stack. The isolation structure extends exceeding opposite sidewalls of the first epitaxial structure.

Abstract: A method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. A portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. A dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. Additional methods are disclosed, as well as semiconductor devices.

Abstract: A light emitting device includes a semiconductor light emitting element which emits excitation light having a peak wavelength in a range of 440 to 450 nm and a fluorescent body layer which is provided on the semiconductor light emitting element, is excited by the excitation light from the semiconductor light emitting element, and contains a first fluorescent body and a second fluorescent body which emit first fluorescent light and second fluorescent light. The first fluorescent light has a peak wavelength in a range of 540 to 575 nm, and the second fluorescent light has a peak wavelength in a range of 590 to 605 nm. In mixed color light of the radiation light, the intensity of the radiation light of the semiconductor light emitting element is 1/10 to 1/60 of the intensity of the combined light of the radiation light from the first fluorescent body and the second fluorescent body.

Abstract: A system and method are provided for repairing an emissive element display. If a defective emissive element is detected in a subpixel, a subpixel repair interface isolates the defective emissive element. The repair interface may be a parallel repair interface with n number of selectively fusible electrically conductive repair nodes, connected in parallel to a control line of the matrix. Alternatively, the repair interface may be a series repair interface with m number of repair nodes, selectively connectable to bypass adjacent (defective) series-connected emissive elements. If the subpixel emissive elements are connected in parallel, and a defective low impedance emissive element is detected, a parallel repair interface fuses open a connection between the defective emissive element and a matrix control line. If the subpixels include series-connected emissive elements, and a high impedance emissive element is detected, a series repair interface forms a connection bypassing the defective emissive element.

Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

Abstract: An optical filter includes a near-infrared absorbing layer including a first material, the first material being configured to absorb light in a first wavelength spectrum belonging to a near-infrared wavelength spectrum. The optical filter includes a compensation layer adjacent to the near-infrared absorbing layer, the compensation layer including a second material different from the first material. The optical filter includes a metamaterial structure spaced apart from the near-infrared absorbing layer via the compensation layer, the metamaterial structure being configured to absorb or reflect light in a second wavelength spectrum at least partially overlapped with the first wavelength spectrum.

Abstract: In an exemplary embodiment, a piezoelectric ceramic composition is an alkali niobate-based piezoelectric ceramic composition whose primary component is a compound expressed by the general formula LixNayK1-x-yNbO3 (where 0<x<1, 0<y<1, and x+y<1), and which contains 100 ppm or more but less than 1000 ppm of fluorine by mass. The alkali niobate-based piezoelectric ceramic composition demonstrates good properties even when sintered at low temperature.

Abstract: A semiconductor package including a semiconductor chip on a package substrate, a transparent substrate on the semiconductor chip, an attachment dam between the semiconductor chip and the transparent substrate, the attachment dam extending along an edge of the semiconductor chip, a first molding layer on the package substrate and surrounding a side surface of the semiconductor chip and including a first epoxy resin, and a second molding layer on the package substrate and filling a space between the semiconductor chip and the first molding layer and including a second epoxy resin. The first epoxy resin includes a first filler containing at least one of silica or alumina. The second epoxy resin includes a second filler containing at least one of silica or alumina. The content of the second filler in the second epoxy resin is greater than a content of the first filler in the first epoxy resin.

Abstract: An image sensor package includes a package substrate; an image sensor chip disposed on the package substrate; a dam structure disposed on the image sensor chip and including a dam main body having an opening and a first light absorption layer disposed on an inner wall of the dam main body; a transparent substrate on the dam structure; and an encapsulant contacting the image sensor chip and an outer wall of the dam main body.

Abstract: A system for wafer processing, includes: a frame comprising a frame opening; and a membrane configured to couple to the frame and to cover at least a part of the frame opening, the membrane comprising a membrane opening, wherein the membrane opening has a membrane opening area that is equal to or less than a frame opening area of the frame opening; wherein the membrane is configured for coupling with the wafer, wherein when the wafer is coupled with the membrane, the wafer covers the membrane opening, and wherein the membrane is configured to maintain the wafer at a certain position with respect to the frame; and wherein the membrane opening area is less than a total area of the wafer.

Abstract: A system for wafer processing, includes: a frame comprising a frame opening; and a membrane configured to couple to the frame and to cover at least a part of the frame opening, the membrane comprising a membrane opening, wherein the membrane opening has a membrane opening area that is equal to or less than a frame opening area of the frame opening; wherein the membrane is configured for coupling with the wafer, wherein when the wafer is coupled with the membrane, the wafer covers the membrane opening, and wherein the membrane is configured to maintain the wafer at a certain position with respect to the frame; and wherein the membrane opening area is less than a total area of the wafer.

Abstract: A computer system and computer-implemented techniques for determining and presenting improved seeding rate recommendations for planting seeds in a field are provided. In an embodiment, a computer-implemented method includes receiving digital data representing planting parameters including seed type information and planting row width, and retrieving a set of seeding models based upon the planting parameters, where each of the seeding models includes a regression model defining a relationship between plant yield and seeding rate on a specific field. The method also includes generating an empirical mixture model as a composite distribution of the set of seeding models, generating a seeding rate distribution for the planting parameters based upon the empirical mixture model, and calculating a seeding rate recommendation based on the seed rate distribution. The method then also includes planting plant seeds in the specific field consistent with the seeding rate recommendation.

Abstract: A transistor in an embodiment includes an oxide semiconductor layer on a substrate, the oxide semiconductor layer including a first region and a second region, a first gate electrode including a region overlapping the oxide semiconductor layer, the first gate electrode being arranged on a surface of the oxide semiconductor layer opposite to the substrate, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a first oxide conductive layer and a second oxide conductive layer between the oxide semiconductor layer and the substrate, the first oxide conductive layer and the second oxide conductive layer each including a region in contact with the oxide semiconductor layer.

Abstract: A spliced micro light-emitting-diode display panel includes multiple circuit boards spliced with each other and multiple micro light-emitting-diode modules. Each circuit board includes at least one driver IC. The micro light-emitting-diode modules are disposed separately on each circuit board and are electrically connected to the driver IC. Each micro light-emitting-diode module includes multiple light-emitting-diode units arranged in an array. On each circuit board, the driver IC drives the light-emitting-diode units of the micro light-emitting-diode modules to emit light. There is a first gap between any adjacent two of the light-emitting-diode units on any adjacent two of the circuit boards, and there is a second gap between any adjacent two of the light-emitting-diode units on each micro light-emitting-diode module, and the first gap is smaller than the second gap.

Abstract: A method for fabricating a three-dimensional (3D) static random-access memory (SRAM) architecture using catalyst influenced chemical etching (CICE). Utilizing CICE, semiconductor fins can be etched with no etch taper, smooth sidewalls and no maximum height limitation. CICE enables stacking of as many nanosheet layers a desired and also enables a 3D stacked architecture for SRAM cells. Furthermore, CICE can be used to etch silicon waveguides thereby creating waveguides with smooth sidewalls to improve transmission efficiency and, for photon-based quantum circuits, to eliminate charge fluctuations that may affect photon indistinguishability.