Abstract: The patent application relates to a PN junction as well as the preparation method and use thereof. Said PN junction comprises a p-type CIGS semiconductor thin film layer and an n-type CIGS semiconductor thin film layer, wherein the n-type CIGS semiconductor thin film layer comprises or consists essentially of elements Cu, In, Ga and Se, where the Cu to In molar ratio is within the range of 1.1 to 1.5, and has a chemical formula of Cu(InxGa1-x)Se2, where x is within the range of 0.6 to 0.9. The patent application further relates to a semiconductor thin film element comprising said PN junction, in particular a photodiode element, and a photoelectric sensing module comprising said semiconductor thin film element as well as the various uses thereof.

Abstract: A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.

Abstract: A display device having an improved light-extraction efficiency and a reduced color sense variation according to a viewing angle includes a pixel electrode on a substrate, an insulating layer defining an emission area via an opening that covers edges of the pixel electrode and exposes a center portion of the pixel electrode, a first light extraction pattern on the pixel electrode, the first light extraction pattern having a side surface inclined at a first angle, and a second light extraction pattern surrounding the first light extraction pattern on an outer portion of the first light extraction pattern, the second light extraction pattern having a side surface inclined at a second angle that is less than the first angle.

Abstract: A system receives a predictive model and receives one or more runtime constraints. The system generates a directed acyclic graph (DAG) of the predictive model indicating dependencies. The system compiles the predictive model into first instructions for a first processor based on the one or more runtime constraints and the DAG. The system packages first instructions, the one or more runtime constraints, and the DAG of the predictive model in a first binary. The system recompiles the predictive model into second instructions for a second processor based on the runtime constraints and the DAG stored in the first processor. The system packages the second instructions, the DAG, and the runtime constraints in a second binary.

Abstract: A semiconductor device is provided. The semiconductor device includes a fin protruding from a semiconductor substrate and a gate structure formed across the fin. The semiconductor device also includes a gate spacer formed over a sidewall of the gate structure. The gate spacer includes a sidewall spacer and a sealing spacer formed above the sidewall spacer. In addition, an air gap is vertically sandwiched between the sidewall spacer and the sealing spacer. The semiconductor device further includes a hard mask formed over the gate structure and covering a sidewall of the sealing spacer.

Abstract: A light emitting device includes a light emitting diode chip, a light transmitting member, a white barrier member, and a conductive adhesive member. The light emitting diode chip has a bump pad formed on the lower surface thereof. The light transmitting member covers the side surfaces and the upper surface of the light emitting diode chip, and the upper surface of the light transmitting member has a rectangular shape having long sides and short sides. The conductive adhesive member is formed to extend through the white barrier member from the bottom of the light emitting diode chip. The upper surface of the conductive adhesive member is connected to the bump pad of the light emitting diode chip, and the lower surface of the conductive adhesive member is exposed at the lower surface of the white barrier member.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect arranged within an inter-level dielectric (ILD) layer. The first interconnect has opposing sidewalls that are both laterally separated from closest neighboring interconnects within the ILD layer by one or more air-gaps along a cross-sectional view. A second interconnect is arranged within the ILD layer. The ILD layer laterally contacts opposing sidewalls of the second interconnect as viewed along the cross-sectional view.

Abstract: A chip-on-film (COF) package includes a film including a reinforcement area, a bending area and a chip mounting area, a conductive pattern layer disposed on the film in the reinforcement area and in the bending area, and at least partially in the chip mounting area, a chip mounted on a portion of the conductive pattern layer in the chip mounting area, a first insulating layer having a first elastic modulus and extending over the conductive pattern layer in the reinforcement area, and a second insulating layer having a second elastic modulus and extending over the conductive pattern layer in the bending area, wherein the first elastic modulus is greater than the second elastic modulus, and the film is intact in the chip mounting area.

Abstract: The present technology relates to an imaging element, a method of manufacturing the imaging element, and an electronic apparatus that make it possible to suppress generation of a void in an infrared cutoff filter layer. The imaging element includes: a light receiving sensor that performs photoelectric conversion of incoming light; a cover glass that protects a top surface side serving as a light incidence surface of the light receiving sensor; a frame that is disposed in an outer peripheral portion between the light receiving sensor and the cover glass, and is formed with use of an inorganic material; and an infrared cutoff filter layer that is formed on an inner side on a same plane as the frame. The present technology is applicable to, for example, an imaging element having a CSP structure, and the like.

Abstract: The present technology relates to an imaging element, a method of manufacturing the imaging element, and an electronic apparatus that make it possible to suppress generation of a void in an infrared cutoff filter layer. The imaging element includes: a light receiving sensor that performs photoelectric conversion of incoming light; a cover glass that protects a top surface side serving as a light incidence surface of the light receiving sensor; a frame that is disposed in an outer peripheral portion between the light receiving sensor and the cover glass, and is formed with use of an inorganic material; and an infrared cutoff filter layer that is formed on an inner side on a same plane as the frame. The present technology is applicable to, for example, an imaging element having a CSP structure, and the like.

Abstract: An optical system (400) including a microlens array (104), an image sensor (108) and a PCB (206). The microlens array (104) is bonded to the image sensor (108) with glue lines (804) or glue drops (802) dispensed around the non-active area (404) of the microlens array (104). The image sensor (108) may be bonded to the PCB (206) with a layer of adhesive material (502) applied only on a central region of the image sensor (108). Alternatively, the image sensor can rest onto a thermally conductive resin layer (109) placed over a stiffener (207), and the image sensor can be attached to the PCB (206) by one or more glue drops (111) or glue lines (113) arranged on at least one side of the image sensor (108) or by an adhesive layer (115) laterally surrounding the image sensor (108). The optical system (400) solves the problem of misalignment between the image sensor and the microlens array caused by changes in temperature.

Abstract: Described herein are systems and methods of utilizing nanochannels generated in the sacrificial layer of a semiconductor substrate to increase epitaxial lift-off speeds and facilitate reusability of GaAs substrates. The provided systems and methods may utilize unique nanochannel geometries to increase the surface area exposed to the etchant and further decrease etch times.

Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package may include a semiconductor chip structure, a transparent substrate disposed on the semiconductor chip structure, a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate, and an adhesive layer interposed between the dam and the semiconductor chip structure. The semiconductor chip structure may include an image sensor chip and a logic chip, which are in contact with each other, and the image sensor chip may be closer to the transparent substrate than the logic chip.

Abstract: A radiation-emitting component (1) is specified with a carrier (2) having a cavity (9), a radiation-emitting semiconductor chip (3) which is arranged on a bottom surface delimiting the cavity (9) and which is configured to generate primary electromagnetic radiation, and a first reflector layer (6) arranged above a top surface of the semiconductor chip (3), wherein the carrier (2) is transparent in places to the primary electromagnetic radiation, and the semiconductor chip (3) is spaced apart from at least one side surface delimiting the cavity (9).

Abstract: A display panel and a manufacturing method of the display panel are provided. The display panel includes: a first substrate, a second substrate disposed opposite to the first substrate, a driving circuit disposed opposite to the first substrate and adjacent to a side of the second substrate, and a color resist layer disposed opposite to the driving circuit and adjacent to a side of the first substrate; wherein the color resist layer includes colorized color resist layers and a colorized quantum dot layer, and the driving circuit is a bottom-emission type light-emitting-diode (LED) driving circuit.

Abstract: A layout structure of flexible circuit board includes a flexible substrate, a chip and a circuit layer. A chip mounting area and a circuit area are defined on a top surface of the flexible substrate. The chip is mounted on the chip mounting area, a space exists between a first bump and a second bump of the chip, and there are no additional bumps between the first and second bumps. A first inner lead, a second inner lead, a first dummy lead and a second dummy lead of the circuit layer are located on the chip mounting area. The first and second inner leads are electrically connected to the first and second bumps respectively. The first dummy lead is connected to the first inner lead and adjacent to the first bump, and the second dummy lead is connected to the second inner lead and adjacent to the second bump.

Abstract: Semiconductor devices having silicon doping for laser splash protection, along with associated methods and systems, are disclosed herein. In one embodiment, a semiconductor device includes a silicon layer and a circuitry layer with a plurality of semiconductor devices. A doped silicon region is formed on a front side of the silicon layer upon which the circuitry layer is deposited. The doped silicon region is positioned under the circuitry layer. The doped silicon region has a dopant concentration of at least 1015 cm?3.

Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.

Abstract: A Complementary Metal Oxide Semiconductor (CMOS) wavefront sensor including a sensor element having an array of photodiodes and a passivation layer covering the sensor element. The sensor further includes a binary lens formed in the passivation layer and arranged to focus incident light onto the sensor element.