Abstract: A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

Abstract: An image capturing device unit includes a multilayer substrate, an image capturing device mounted on one face of the multilayer substrate, and components mounted on the other face of the multilayer substrate. The multilayer substrate includes electrodes to electrically connect the image capturing device and the multilayer substrate, vias that electrically connect the electrodes and the components, first wiring electrically connected to the vias, second wiring on layers of the multilayer substrate, and a non-wired region that insulates the vias and the first wiring from the second wiring on each of the layers. The vias are located in the multilayer substrate so that, on a projection plane given when the multilayer substrate is viewed in a layering direction of the multilayer substrate, there is no area in which the non-wired region overlaps with a region where the image capturing device is arranged throughout the layers.

Abstract: Disclosed herein are isolation regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include: a first region including silicon; a second region including alternating layers of a second material and a third material, wherein the second material includes silicon and germanium, the third material includes silicon, and individual ones of the layers in the second region has a thickness that is less than 3 nanometers; and a third region including alternating layers of the second material and the third material, wherein individual ones of the layers in the third region has a thickness that is greater than 3 nanometers, and the second region is between the first region and the third region.

Abstract: A method of fabricating a solid-state image sensor, including steps of forming a second type doped semiconductor layer and a semiconductor material layer sequentially on a first type doped semiconductor substrate to constitute a photoelectric conversion portion, forming a multilayer structure on the semiconductor material layer, wherein a refractive index of the multilayer structure gradually decreases from a bottom layer to a top layer of the multilayer structure and is smaller than a refractive index of the semiconductor material layer, and performing a photolithography process to the multiplayer structure and the photoelectric conversion portion to form multiple micro pillars, wherein the micro pillars protrude from the semiconductor material layer and are isolated by recesses extending into the photoelectric conversion portion.

Abstract: A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap.

Abstract: Systems and methods for organic semiconductor devices with sputtered contact layers are provided. In one embodiment, an organic semiconductor device comprises: a first contact layer comprising a first sputter-deposited transparent conducting oxide; an electron transport layer interfacing with the first contact layer; a second contact layer comprising a second sputter-deposited transparent conducting oxide; a hole transport layer interfacing with the second contact layer; and an organic semiconductor active layer having a first side facing the electron transport layer and an opposing second side facing the hole transport layer; wherein either the electron transport layer or the hole transport layer comprises a buffering transport layer.

Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

Abstract: A display device includes: a display module; a driving chip assembly electrically connected to the display module and including a driving chip and a heat dissipator at least partially surrounding the driving chip; and a main circuit board electrically connected to the driving chip assembly and contacting the heat dissipator.

Abstract: A light emitting device including a plurality of element structures each including a submount, a light emitting element, and a light transmissive member, in this order. The light emitting device further includes a first cover member holding the element structures by covering lateral faces of each of the element structures.

Abstract: A semiconductor device includes a substrate having a first region and a second region, first and second nanowires disposed sequentially on the substrate in the first region, and extending respectively in a first direction, third and fourth nanowires disposed sequentially on the substrate in the second region, and extending respectively in the first direction, a first inner spacer between the first nanowire and the second nanowire, and including hydrogen of a first hydrogen mole fraction, and a second inner spacer between the third nanowire and the fourth nanowire, and including hydrogen of a second hydrogen mole fraction that is greater than the first hydrogen mole fraction.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin.

Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.

Abstract: A semiconductor memory device including: a common source line; a substrate on the common source line; a plurality of gate electrodes arranged on the substrate and spaced apart from each other in a first direction perpendicular to a top surface of the common source line; a plurality of insulation films arranged among the plurality of gate electrodes; a plurality of channel structures penetrating through the plurality of gate electrodes and the plurality of insulation films in the first direction; and a plurality of residual sacrificial films arranged on the substrate and spaced apart from each other in the first direction, wherein the plurality of gate electrodes are disposed on opposite sides of the plurality of residual sacrificial films.

Abstract: A semiconductor apparatus comprising a first substrate, a second substrate coupled with the first substrate via an insulating member, a third substrate coupled to the first substrate and disposed on the opposite side to the second substrate and a conductive layer including an electrode disposed between the first and second substrate is provided. A through via is disposed so as to pass through the second substrate and a part of the insulating member to reach the electrode. An opening is arranged overlapping the electrode in the first substrate and a part of the insulating member. First and second resin layers are disposed between the electrode and the third substrate, and the first resin layer is disposed within the opening, is disposed between the electrode and the second resin layer and has a different Young's modulus from the second resin layer.

Abstract: An optoelectronic assembly includes an integrated circuit (IC) chip including, on its front side, a photoconversion region and first electrical contact pads disposed alongside the photoconversion region. A circuit substrate contains a cavity into which the IC chip is inserted through the lower side and has a window opening through the upper side in communication with the cavity such that the photoconversion region of the IC chip is exposed through the window. The circuit substrate includes electrical circuit traces, which include second electrical contact pads disposed within the cavity alongside the window so as to contact the first electrical contact pads on the front side of the IC chip within the cavity. A base includes a stiff, heat-conducting material, to which the lower side of the circuit substrate is fixed. A malleable heat-conducting layer is compressed between the rear side of the IC chip and the base.

Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.

Abstract: A semiconductor device includes: an alternating stack that is disposed over a lower structure and includes gate electrodes and dielectric layers which are staked alternately; a memory stack structure that includes a channel layer extending to penetrate through the alternating stack, and a memory layer surrounding the channel layer; a source contact layer in contact with a lower outer wall of the vertical channel layer and disposed between the lower structure and the alternating stack; a source contact plug spaced apart from the memory stack structure and extending to penetrate through the alternating stack; and a sealing spacer suitable for sealing the gate electrodes and disposed between the source contact plug and the gate electrodes. The sealing spacer has an etch resistance that is different from an etch resistance of the dielectric layers.

Abstract: A semiconductor device structure includes a fin structure, a semiconductive capping layer, an oxide layer, and a gate structure. The fin structure protrudes above a substrate. The semiconductive capping layer wraps around three sides of a channel region of the fin structure. The oxide layer wraps around three sides of the semiconductive capping layer. A thickness of a top portion of the semiconductive capping layer is less than a thickness of a top portion of the oxide layer. The gate structure wraps around three sides of the oxide layer.

Abstract: A method of fabricating a polymer wire according to the present embodiment includes preparing an electrode platform having a micro gap, forming a plurality of single polymer wires on the electrode platform, and a heat treatment operation of aggregating the plurality of single polymer wires to form an aggregated polymer wire.

Abstract: A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.