Abstract: Disclosed is a digital filter having phase-adjustment ability, and more particularly to a digital filter system which can restore the phase of data transmitted via digital radio communication and thereby enhances the noise-immunity of data and the correct bit decision. The digital filter mainly includes a hold back data unit, a digital filter unit, and a signal phase modify unit to remove noises in the signals and to modify and restore correct digital wave-form signals. The digital filter having phase-adjustment ability is suitable for use in digital radio phones, pagers, etc. commonly found in the radio communication systems.

Abstract: A Differential receiver of direct sequence spread spectrum signals, wherein, the intermediate frequency stage comprises N filtering and amplifying channels in N separate bands. The amplification of a channel is adjusted so that the power levels delivered by the channels correspond to a predetermined power distribution law.

Abstract: A digital transmission system, such as a mobile radio system, having a transmitter for transmitting codewords which are derived from a digital signal, and a receiver for receiving codewords, the receiver including a decoder with a prediction filter which is excited by an input signal to produce an estimated digital signal. To improve reconstruction of the digital signal in the event of disturbances, the decoder includes a first switching circuit for switching off the input signal of the prediction filter when a disturbed codeword is received, and a second switching circuit for switching substitute values formed from previous values of the estimated digital signal instead of the estimated digital signal when the input signal is switched off.

Abstract: This receiver comprises a signal processor using the correlation of the received composite signal with early/late, locally generated pseudo-random codes. The code generator sends its signals to a delay line whose evenly spaced out outputs (E2, E1, P, L1, L2) are combined according to the relationship:c=E2-2E1+2L1-L2before being sent to one of the correlators (C2) while the other (C1) receives the punctual signal (P). This especially reduces the positional error due to the multiple-path delays.

Abstract: The present invention solves the conventional problems and has an object to provide a matched filter system of high process in speed, a small size and low electric power consumption. The matched filter circuits of each matched filter set is allocated different n combinations of M/n digits selected from the M length PN code sequence picking one out of every n digits, cyclically performs sampling every 1 chip time duration the input signals to be inputted to each set constructed by matched filter circuits by n sets each of which including n matched filter circuits, and calculates the sum of outputs of all matched filter circuits.

Abstract: The FSK modulator for modulating binary data of the present invention has an object to provide an FSK modulator which can operate at a stable frequency also when a discontinuous data row is entered. The FSK modulator comprises a PLL (phase locked loop) in which binary data is entered at two types of voltage levels different each other, an oscillation output of the PLL treated as output data of the modulator, allows a voltage at an almost-intermediate level to the PLL instead of binary data when the binary data has not been entered.

Abstract: A signal equalizer for equalizing a waveform of a digital data sequence includes a discriminator for discriminating average measurement levels at plural frequencies of the digital data sequence, an error operating unit for finding the ratio or difference between an equalizing target average level which correspond to the plural frequencies that has been found in advance and an average level obtained by the discriminator and a controller for controlling an equalizing characteristic of the equalizer based on the error information obtained by the error operating unit.

Abstract: A bipolar-clock monitor circuit includes a first shift register shifting positive-polarity pulse signal according to the negative-polarity pulse signal to produce a i-bit-shift signal and a j-bit-shift signal. The integers i and j are determined based on the period ratio of a main clock and a subclock included in the bipolar clock signal so that the i-bit-shift signal is identical with the j-bit-shift signal when the bipolar clock signal is normal. The non-coincidence determination circuit checks whether the i-bit-shift signal coincides with the j-bit-shift signal and produces a disturbance detection signal when the i-bit-shift signal does not coincide with the j-bit-shift signal.

Abstract: A method and a circuit for simple clock recovery from multi-level at high transmission rates. The circuit is compatible with standard PLL-type clock recovery techniques for NRZ and generalized two-level signalling. The timing information is extracted from a single threshold crossing, irrespective of the number of levels (M) of the signal. This was verified to provide sufficient spectral information for the proper operation of a clock recovery PLL. The threshold may be programmed for various line codes.

Abstract: A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.

Abstract: A communication device (104) comprises a receiver circuit (108) receiving a modulated receive signal. A reference oscillator (132) generates a first clock signal at a first frequency, the first clock signal having harmonics. Circuitry (130) coupled to the reference oscillator and to the receiver responds to the first clock signal to produce a signal used by the receiver to reduce the frequency of the modulating signal. A frequency spreading circuit (134) is also coupled to the reference oscillator to modulate the first clock signal with a frequency spreading signal to produce a modulated clock signal including modulated harmonic frequency components. The frequency spreading circuit selectively combines the frequency spreading signal and the first clock signal. A control circuit (114) controls the frequency spreading circuit to modulate first clock signal with the frequency spreading signal when the selected received signal includes a harmonic of the first clock signal.

Abstract: A digital phase detector which generates low jitter when the phase-locked-loop is in lock. A delay line, combined with an UP/DOWN phase detector causes substantial overlap in the UP and DOWN signals from the detector. When the PLL is in lock, the overlapping signals substantially cancel each other out, minimizing the variations in the output frequency. Two approaches are disclosed: one delaying the UP signal sufficiently to overlap the DOWN signal, the other using a delay and an exclusive OR gate to generate the DOWN signal.

Abstract: A system and method includes an encoder and noise predictive Viterbi detector tuned such that error events with small values of the unique distance metrics are eliminated so that the error rate is enhanced. The system includes an encoder, a modulator, a PR channel and a detector. An input signal is input to the encoder. The encoder preferably encodes the input string with an even weight code to generate a code string thereby providing high code rates that are easy to implement. The output of the encoder is coupled to the input of the PR channel. The PR channel preferably comprises a filter and a noise source coupled to form a channel, a sampler, a low pass filter and an equalizer. The output of the channel is input to the low pass filter. The output of the low pass filter is coupled by the sampler to the input of the equalizer. Finally, the output of the equalizer is coupled to the input of the detector.

Abstract: An offset circuit (2) detects an offset word serving as a synchronization pattern. By being triggered by the detection, main and subordinate synchronization detection circuits (5 and 6) detect the periodicity of the offset word only during a predetermined backward guard period. Both synchronization detection circuits (5 and 6) detect offset words at different timings. Therefore, if one synchronization detection circuit (5 or 6) fails in detection of synchronization, it is possible to use a detection result of the other synchronization detection circuit (5 or 6). Moreover, received data during the backward guard period is stored in a data memory (11). Therefore, it is possible to use the stored data as received data after detection of synchronization. Even after establishment of synchronization, the synchronization detection circuit (5 or 6) continuously detects the periodicity of an offset word at a timing different from an established timing.

Abstract: A circuit for transmitting data in asynchronous transfer mode includes two phase-locked loops associated with a transmission unit and a reception unit, respectively. Each PLL is provided with a voltage-controlled oscillator formed by an astable multivibrator. The reference current fixing the free oscillating frequency of the multivibrator that is associated with the reception unit corresponds to the frequency adjustment current of the multivibrator that is associated with the transmission unit. Each VCO includes a differential amplifier, connected as a voltage-to-current converter, receiving two voltages corresponding to the phase error of the loop with which it is associated, and providing a frequency adjustment current of its astable multivibrator.

Abstract: A digital data signal reading and reproducing apparatus which can accurately read and reproduce a digital data signal recorded on a recording medium at a high density. There is performed a Viterbi decoding process in which a code series pattern which the digital data signal can take is subjected to the convolution arithmetic calculation by means of discrete impulse responses h(i) obtained by performing the discrete inverse Fourier transformation on the frequency characteristics of a signal recording and reproducing system constructed by the recording medium and its reading device and the results of the convolution arithmetic calculation are made to be the predicted values.

Abstract: A PLL-mode radiofrequency module capable of being connected to a transmitter of any kind. The PLL-mode module is provided therein with a CPU, which functions to vary a waveform of a PPM signal fed thereto from a transmitter body so as to permit a pulse duty ratio of the PPM signal to be about 50%. The PPM signal thus varied is fed to a modulation circuit and then subjected to FSK modulation, so that a PLL oscillator constituted by a PLL circuit and a modulation circuit or voltage control oscillator generates a frequency as indicated by a rotary switch. A carrier frequency controller thus constructed is arranged on a side of the PLL-mode radiofrequency module rather than the transmitter body, so that the PLL-mode radiofrequency module may be connected to a transmitter of any kind.

Abstract: The present invention has an object to provide a matched filter circuit which is possible to synchronize a spreading code with an input signal. A matched filter according to the present invention samples input signal in response to three clocks from the first to the third shifted by a half cycle of a sampling signal so as to judge whether the sampling clock is ahead or behind of the input signal according to signs of input signal sampled. One clock is selected to be the sampling clock.

Abstract: The system and method determines whether the expected location of the pilot channel in the PN code sequence (i.e. the PN code phase offset) has been detected in an initial search window centered on the expected pilot PN code phase offset. If not, a new search window is defined which is advanced in the PN code sequence from the initial search window. If the actual location of the pilot channel in the PN code sequence is not detected in the new search window, a subsequent search window is defined which is retarded in the PN sequence from all previous search windows. This iterative "spiral" searching method is repeated with increasingly divergent alternating advanced and retarded search windows until either the actual location of the pilot channel in the PN code sequence is detected, or a predetermined maximum number of iterations has occurred.

Abstract: A digital phase-lock loop network that provides input and output clock signals to a digital data receiving system generally, and particularly to a data buffer contained therein, is disclosed. The digital phase-lock loop network provides bit-clock synchronization using a fixed input clock and an output clock having a variable frequency that is adjusted to correspond to the average input rate of the data samples into the data buffer. The digital phase-lock loop network allows the data buffer to be operated as a temporary storage device maintaining a nominal number of data samples therein at all times by avoiding any overflow and underflow data handling conditions that may otherwise cause loss of data. The digital phase-lock loop network of the present invention is particularly suited for the Eureka-147 system which has become a worldwide standard for digital audio broadcasting (DAB) technology.