Abstract: An input information signal is phase-modulated in a DQPSK (differentially encoded quadrature phase shift keying) modulation system. The resultant modulated signal is supplied to an input terminal of a first multiplier. A first M-bit random number generator receives transmission timing data and initial value data from a first initial value generator and generates an M-bit random numbers beginning at the initial value data. A first phase generator generates phase data corresponding to the random number and supplies the phase data to the other input terminal of the first multiplier. A first multiplier generates a first multiplied signal by multiplying the modulated signal from the phase modulator and the phase data from the first phase generator. The first multiplied signal is transmitted through a wireless or wire transmission path. A reception signal from the transmission path is supplied to one input terminal of a second multiplier.

Abstract: A digital PLL circuit has a data sampling circuit for sampling input data in response to N phase clocks in the direction of time. The phase of the clock corresponding to, among the sampled data, the data in which edges are evenly detected is used as a first phase or reference clock. The successive clocks following the first phase clock are used as a second phase clock to an N-th phase clock. The sampled data are rearranged in synchronism with the first phase clock to the N-th phase clock to turn out first phase to N-th phase sampled data. The first phase to the N-th phase sampled data are latched by the first phase clock. The pattern of data received in bursts is identified every period on the basis of the latched first to N-th phase data. Among the latched first to N-th sampled data, the data to be identified are selected. These data are retimed in synchronism with the first phase clock so as to output a phase clock signal.

Abstract: A method for converting binary data into a multilevel signal where the binary data includes m data, or symbols, per group unit which have n bits per data. The multilevel signal includes m time slots, or symbol periods, and m+1 levels per basic period. The m time slots include 0th to m-1 slots. The m+1 levels include 0th to m-1th levels and an upper standard level above the m-1th level. The basic period is alternately and consecutively defined as A type and B type. A type data at a predetermined location is defined as an index data. When the binary data is converted into the multilevel signal, the index data is assigned to the Tth time slot taking the 0th level in the A type basic period and upper standard level in the B type basic period corresponding to a value T of the original index data in binary digit. Other binary data j, or normal data, are allocated to each time slots except the Tth time slot for the index data after converted into the multilevel signal with level values L.sub.

Abstract: A class 2 or UART data communication bus is subject to disruption by induce high frequency currents because of an impedance mismatch between a passive pull-up or pull-down resistor and a lower impedance active current sourcing or sinking stage. An impedance reduction circuit across the passive resistor balances the impedance in the presence of high frequency noise. The impedance reduction circuit is operative when it senses a bus line voltage slew rate greater than that caused by data pulses and a voltage change greater than one diode drop.

Abstract: The relates to locking the phase of output signal (Ys) relative to an input signal (Ye). A first frequency correction signal (Yr1) is obtained by integrating a signal representative of an error of said phase relative to a reference defined by the input signal. It then cooperates with a second frequency correction signal (Yr2) to correct the frequency of an oscillator (VCO) supplying the output signal. The second frequency correction signal is obtained with the help of an adjustment signal (Yg) by integrating an error of the first frequency correction signal (Yr1) relative to said adjustment signal. The adjustment signal may itself be obtained by integrating a frequency error. The invention is particularly applicable to telecommunications systems.

Abstract: A sync pattern detecting circuit detects a sync pattern from the input data to output a sync pattern detecting signal. A frame counter counts clock signals for the bit number of one frame to output a frame count signal. A sync manage circuit sets a window time area therein, and outputs a sync signal when the sync pattern detecting signal is input in the window time area. The width of the window time area is variable. The width of the window time area is controlled at timings at which the sync pattern detecting signal and the frame count signal are input.

Abstract: In a synchronizing circuit receiving a bit stream including a synchronous pattern and various kinds of information bits, for outputting a synchronous signal, there is provided a synchronous pattern register which is previously set with known information bits of the layer, the bit rate and the sampling frequency. A synchronous pattern detecting circuit is configured not to recognize as a synchronous pattern, a synchronous pattern having the values other than previously set values. With this arrangement, it is possible to remarkably reduce probability that a quasi synchronous pattern is detected as the synchronous pattern, and therefore, it is possible to minimize missing of sound corresponding to the digital audio signal.

Abstract: A spread spectrum communication apparatus comprises a correlator for correlating a received signal and a reference signal, a synchronizing circuit for synchronizing codes for spread spectrum communication according to a correlation output of the correlator, a controller for controlling a transmission power according to the output of the correlator, and a detector for detecting the output of the correlator. The synchronizing circuit synchronizes the codes according to the output of the correlator detected by the detector. The controller controls the transmission power according to the output of the correlator detected by the detector.

Abstract: A plurality of biphase modulators (42) each modulate a sinusoidal radio frequency signal based upon a corresponding one of a plurality of bits contained in a time-dependent data word. The biphase modulators (42) form a plurality of biphase modulated signals which are communicated to a summing network (40). The summing network (40) contains a plurality of attenuators (44) which attenuate the modulated signals to form a plurality of attenuated signals. The summing network (40) combines the attenuated signals to form a radio frequency signal.

Abstract: A built-in system and method is provided that measures Phase Lock Loop (PLL) output clock error. An edge sorting circuit is utilized to measure jitter between corresponding transition edges of a measured clock and a reference clock, and then stores the value in an N bit word. A decoder circuit reads in the value and increments a corresponding counter. A state machine then reads the counters, processes the information and outputs one or more PLL clock error values.

Abstract: The invention relates to a method and apparatus for synchronization of transmitters and receivers in digital transmission systems of the OFDM type. The system uses FFT technique to carry out the modulation and demodulation procedures. According to the invention, the transmitter sends synchronization frames with known frequencies and phase positions and with known time intervals in certain time slots. The receiver carries out a series of time-shifted FFT operations over the time position where the synchronization frame is calculated to be. For each operation, a cross-correlation is carried out in the frequency plane of the output signal with the known frequency function of the synchronization frame. The correlation maximum is detected, and this determines the time slot which contains the synchronization frame, whereupon this is used as time base for the following data frames.

Abstract: A phase shift correcting apparatus of a sync detector in a satellite broadcasting reception system corrects a phase shift of 180.degree. which makes output data after demodulation be absolutely different from an original data such that 47 sync is phase-shifted by 180.degree. to be detected as B8 sync data. For this, the number of B8 data and 47 data of input data is counted in a comparator and a counter to determine whether the phase shift of 180.degree. occurs or not, and data involving the phase shift is converted to have a normal data value when it is determined that the phase shift occurs, thereby improving reliability of a satellite broadcasting receiver and solving the problem of the different data output.

Abstract: A T1 digital PCM signal frame synchronizer includes a RAM memory for storing a complete extended superframe of received data, a pattern detector for detecting patterns in the memory that match a predetermined frame alignment signal, and a plurality of address pointer registers and associated counters. A given address within the RAM corresponds to a particular bit position within the received data. The first time that a pattern is detected at a given address within memory, that address is stored into a register, and its associated counter set to one. Subsequent pattern matches and violations at that address cause the counter to increment and decrement, respectively. A register whose counter value decrements down to zero becomes available for storing a new address. In-sync is declared when any counter exceeds an in-sync threshold. Out-of-sync is declared when that counter falls to an out-of-sync threshold or below.