Abstract: A digital filter (200) suitable for use in a CDMA or other burst-mode communication device (100) employs precombining of filter coefficients to reduce filter complexity and power dissipation. The digital filter (200) includes a coefficient storage circuit (216) for storing the precombined coefficients, a selection circuit (212) for selecting appropriate precombined coefficients in response to the input signal and a combining circuit (214) for combining the appropriate precombined coefficients to produce a filtered signal.

Abstract: Within a microprocessor, multiple synchronous clock signals of arbitrary integer and non-integer ratios are produced with conventional digital divider circuitry. The various integer and non-integer clock signals can be provided to processor circuitry, bus circuitry, and coupled memory circuitry. Non-integer ratio clock signals can be produced out-of-phase with the system clock signal.

Abstract: A digital delay lock loop for generating frequency multiples of an input clock signal includes a programmable digital oscillator, a phase comparator, a programmable counter and delay control logic. The programmable digital oscillator is a ring connected programmable delay line and inverter which together generate an output clock signal having a frequency which depends upon the time delay of the programmable delay line. The phase comparator compares the phase of the output clock signal to that of a reference clock signal and generates a phase error signal which represents the phase difference between such signals. The programmable counter, programmed and reprogrammed with the arrival of every reference clock signal pulse, counts the output clock signal pulses to generate a count signal.

Abstract: A method for improving a radio location system based on time-of-arrival. Time-of-arrival radio location systems are limited in ultimate accuracy by signal-to-noise ratio and by the time varying multipath environment in which they must operate. The present invention teaches techniques which maintain a high signal-to-noise ratio while identifying a feature of the received signal which is least affected by multipath. The technique uses correlation peak/envelope information to estimate the leading edge of the correlation function, then enhances discrete samples at the leading edge of the correlation function to yield high signal-to-noise ratio readings. The present invention can reduce required transmitted bandwidth, increase system resolution and accuracy by twenty to one, and maintain high message traffic throughput.

Abstract: A differential delay buffer includes a variable delay buffer unit, the variable delay buffer unit having a differential stage followed by a variable hysteresis stage. A plurality of variable delay buffer units can be cascaded together, in each variable delay buffer units a part of the required delay being effected. The variable hysteresis stage is responsive to the signal level at a second differential stage output to recover the signal at a first differential signal output from the variable delay buffer unit and is responsive to the signal level at a first differential stage output to recover the signal at the second delayed differential signal output for the variable delay buffer unit. The differential delay buffer can be included in a delay locked loop in data transmission applications.

Abstract: A CDMA communication method and system including a receiver that operates in one of two modes, switching between non-coherent and coherent reception on the basis of a channel quality indicator. An important application of this technique would be over the reverse link (from user to base station) of a CDMA system based on the IS-95 cellular standard or the PN-3384 PCS standard.

Abstract: A diversity receiver respectively receiving signals in two branches includes two demodulating sections for producing respective amplitude and phases of received signals at a unit of symbol. The receiver includes a memory access section for producing an amplitude ratio of the amplitude of the received signals and a phase difference between the phases of the received signals. The receiver further includes a storage section for storing at least one relative phase difference between a phase of a vector-combined signal combined based on the received signals and one of the phases of the received signals for an address given by the amplitude ratio and the phase difference of the received signals. The phase of the vector-combined signal is previously calculated based on the amplitude ratio, the phase difference, and the one of the phases of the received signals.

Abstract: A new modem architecture that substantially minimizes the cost of adding features to the modem, and substantially minimizes the time overhead associated with the slave-like interface between the modem controller and the modem signal processor. The architecture enables the signal processor to directly access the controller's memory resources so that the signal processor can make most efficient use of its own internal expensive high-speed memory.

Abstract: A dual locked loop is disclosed comparing preferably a GPS signal with an E1 signal and the E1 signal with the output of the loop. The GPS signal is low pass filtered to provide a low pass filtered GPS versus E1 signal that is used as a calibration for a closed loop having a second low pass filter for filtering the comparisons of the E1 and the output signal. By appropriately selecting the filter parameters, the output stability can track the stability of the local oscillator driving the NCO for short term stability, the medium term stability of the E1 signal and the long term stability of the GPS signal.

Abstract: A matched filter contains a plurality of auxiliary sampling and holding circuits in addition to a main sampling and holding circuit containing multiple unit sampling and holding circuits. An auxiliary sampling and holding circuit is used to hold an input voltage, which would ordinarily be held by a unit sampling and holding circuit, when the unit sampling and holding circuit is being refreshed. By holding a part of the analog input voltage in the auxiliary sampling and holding circuits, refreshing is performed without decreasing the overall calculation speed.

Abstract: Apparatus for reducing electromagnetic radiation from a differentially driven transmission line for high data rate communication in a computerized tomography system is provided. The apparatus comprises a carrier generator, for generating a carrier signal having a predetermined carrier bandwidth. A modulator is respectively coupled to the carrier generator for receiving the carrier signal and for receiving an externally-derived data signal to produce a modulated output signal. The carrier bandwidth is sufficiently broad relative to a predetermined inspection bandwidth for substantially reducing the level of electromagnetic energy being measured over the inspection bandwidth.

Abstract: Delay locked loop intended to be used in a receiver of signals emitted by a GPS satellite, comprising a pseudo-random code generator (35), a local oscillator (34), a modulator (14) for modulating said pseudo-random code with the output signal of said local oscillator (34), a plurality of signal channels (C1, C2, C3) connected to the output of said modulator (14) and each comprising a pass-band filter (48 to 50). A data processing unit (11) is adapted to control the central frequency of the output signal of said local oscillator as a function of the output signal of said signal detection circuit and to control the central frequencies and the bandwidth of said pass-band filters (48 to 50) in several steps during said acquisition phase, so that said pass-band filters divide up, at each step, one of the pass-bands of the preceding step into non-overlapping pass-bands.

Abstract: A transmitting and receiving signal switching circuit for a wireless communication is disclosed, in which, in an initial portion of a wireless communication apparatus, i.e., in a high output amplifier and in a low noise amplifier, when signals are transmitted, the power source of the low noise amplifier is disconnected, and when signals are received, the power source of the high output amplifier is disconnected, thereby switching the transmitting and receiving signals. According to the present invention as described above, a switching circuit is used, so that the communication apparatus would become compact and convenient, and that the power consumption can be reduced. Further, the deterioration of the involved components can be prevented, thereby extending the life expectancy of the apparatus. Further, the number of the components are reduced, so that the manufacturing cost can be saved.

Abstract: A digital data receiver includes tunable analog components having variable parameters that are responsive to the bit error rate (BER) of the decoded digital data. The analog components include a quadrature generator having a tunable phase shifter, an analog filter having a tunable bandwidth, a tunable magnitude equalizer circuit, a tunable group delay equalizer circuit, and an amplifier having an adjustable gain. The tunable components are controlled by tuning control signals that incorporate digitally-produced fine tuning signals. The digital tuning signals are altered in accordance with realtime changes in the BER.

Abstract: A monolithic device is shown having a number of phase locked loops (PLLs) constructed thereon. At least one of the PLLs is constructed as a multiple loop having an output of one PLL loop tied back to the feedback path of the other loop of the pair. In this manner, tight resolution can be obtained in one loop while the bandwidth of that loop is coarse. The bandwidth of the second loop is tight, thereby giving good resolution to the first loop while still avoiding the problems inherent with noise injection locking from other PLLs on the same device.

Abstract: A digital filter is composed of an FIR filter with a finite tap length and a feedback section. An apparatus for reproducing sound is arranged to use the digital filter. In the feedback section, an output of one of a plurality of delaying units included in the FIR filter is attenuated through the effect of a coefficient multiplier. The attenuated output is fed back to an adder located between adjacent delaying units arranged before the one delaying unit. The feedback section repeats the feedback operation to generate an infinitely continuing impulse response.

Abstract: In a data transmission system having a transmission apparatus and a receiving apparatus through a network which supplies first and second network clock signals to the transmission and receiving apparatus respectively, synchronizing signal generation portions in both apparatus generate first and second periodical signals generated from the first and second network clock signals having a constant phase relation therebetween. The transmission apparatus generates time information indicating a data encoding timing according to a system clock signal of the transmission apparatus and supplies the time information in response to the first periodical signal and transmits the time information with data to be transmitted to the receiving apparatus.

Abstract: A digital phase synchronous circuit includes a phase comparing circuit for outputting a count value according to the result of a phase comparison between an output signal and an externally input reference signal; a frequency regulating circuit for inputting an oscillation signal with a predetermined repetition frequency and controlling the repetition frequency according to the count value to output it as the output signal; and a controlling circuit for controlling the frequency regulating circuit to output the oscillation signal with the predetermined repetition frequency when the input of the reference signal breaks down.

Abstract: A FSK modulator which uses the combination of a state machine and a toggle flip-flop to generate the FSK signals. The state machine has a loop having a predetermined number of states. The number of clock cycles that the state machine takes to traverse the loop depends on the state or level of the signal at the input to the modulator. The flip-flop converts the state machine output signal to a signal having a rectangular waveform.

Abstract: A baseband signal, obtained by quasi-coherent detecting a received signal, is sampled and written as a sequence of baseband signal samples into a buffer memory. For each baseband signal sample read out from the buffer memory, a maximum likelihood sequence estimation part generates a desired symbol sequence and feeds it to a transversal filter having a characteristic based on an estimated impulse response of the transmission path in correspondence with the timing of the baseband signal sample. A phase error between an estimated received signal from the transversal filter and the corresponding baseband signal sample is sequentially detected by a phase error detecting part. The phase error thus obtained is fed to an offset correcting signal generating part, which calculates an estimated offset angular frequency .DELTA..omega..sub.