Abstract: Electric characteristics of a semiconductor device using an oxide semiconductor are improved. Further, a highly reliable semiconductor device in which a variation in electric characteristics with time or a variation in electric characteristics due to a gate BT stress test with light irradiation is small is manufactured. A transistor includes a gate electrode, an oxide semiconductor film overlapping with part of the gate electrode with a gate insulating film therebetween, and a pair of electrodes in contact with the oxide semiconductor film. The gate insulating film is an insulating film whose film density is higher than or equal to 2.26 g/cm3 and lower than or equal to 2.63 g/cm3 and whose spin density of a signal with a g value of 2.001 is 2×1015 spins/cm3 or less in electron spin resonance.

Abstract: An electronic device includes an anisotropic conductive film as a connection material, the anisotropic conductive film being formed from an anisotropic conductive film-forming composition. The anisotropic conductive film-forming composition includes a polycyclic aromatic ring-containing epoxy resin, a fluorene epoxy resin, nano silica and conductive particles.

Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.

Abstract: Disclosed are a light emitting device, a method for manufacturing the same, a light emitting device package, and a lighting system. The light emitting device includes a first conductive semiconductor layer, an active layer comprising a well layer and a barrier layer on the first conductive layer, and a second conductive semiconductor layer on the active layer. The well layer includes a first well layer closest to the first conductive semiconductor layer and having a first energy bandgap, a third well layer closest to the second conductive semiconductor layer and having a third energy bandgap, and a second well layer interposed between the first and third well layers and having a second energy bandgap. The third energy bandgap of the third well layer is greater than the second energy bandgap of the second well layer.

Abstract: An organic light emitting diode (OLED) lighting apparatus includes a light emitting panel including an organic light emitting diode, a housing for housing the light emitting panel, a cover coupled to the housing and covering a front-side edge of the light emitting panel, a plurality of pins disposed between the housing and the light emitting panel and supporting an edge of the light emitting panel, and at least one contact bar disposed between the plurality of pins and a back-side edge of the light emitting panel.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a gate, a channel layer, a gate insulation layer, a source, a drain and a silicon-aluminum-oxide layer. The gate is disposed on a substrate. The channel layer is disposed on the substrate. The channel layer overlaps the gate. The gate insulation layer is disposed between the gate and the channel layer. The source and the drain are disposed on two sides of the channel layer. The silicon-aluminum-oxide layer is disposed on the substrate and covers the source, the drain and the channel layer.

Abstract: An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is deposited in a plurality of the first recesses to form a plurality of first conductive pillars electrically coupled to, and extending generally perpendicular to, the first circuitry layer. At least a second dielectric layer is printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive pillars. A conductive material is deposited in a plurality of the second recesses to form a plurality of second conductive pillars electrically coupled to, and extending parallel the first conductive pillars.

Abstract: An organic light emitting diode (OLED) display includes: a substrate; an organic light emitting diode formed on the substrate; a first inorganic layer formed on the substrate and covering the organic light emitting diode; an intermediate layer formed on the first inorganic layer and covering an area relatively smaller than the first inorganic layer; and a second inorganic layer formed on the first inorganic layer and the intermediate layer, and contacting the first inorganic layer at an edge thereof while covering a relatively larger area than the intermediate layer. A third inorganic layer may be formed on the second inorganic layer so as to contact the second inorganic layer at an edge thereof. At least one of the first, second and third inorganic layers is formed by an atomic layer deposition (ALD) method.

Abstract: A semiconductor memory device includes a first chip and a second chip connected to the first chip physically and electrically, wherein the first chip and the second chip are coupled by through silicon vias (TSVs) formed in a first region, and the first chip and the second chip are coupled by alignment keys formed in second regions.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a thermal attach cluster includes: forming a heat collector having a heat dissipation surface, forming a cluster bridge, having a thermal surface, connected to the heat collector, forming a cluster pad, having an attachment surface, connected to the end of the cluster bridge opposite the heat collector; connecting an integrated circuit to the thermal attach cluster; and forming an encapsulation over the thermal attach cluster with the heat dissipation surface, the thermal surface, and the attachment surface exposed from and coplanar with the encapsulation.

Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.

Abstract: A phase change material comprises GexSbyTez, wherein a Ge atomic concentration x is within a range from 30% to 65%, a Sb atomic concentration y is within a range from 13% to 27% and a Te atomic concentration z is within a range from 20% to 45%. A Ge-rich family of such materials is also described. A memory device, suitable for integrated circuits, comprising such materials is described.

Abstract: A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.

Abstract: A semiconductor arrangement includes a semiconductor body and a power transistor arranged in a first device region of the semiconductor body. The power transistor includes at least one source region, a drain region, and at least one body region, at least one drift region of a first doping type and at least one compensation region of a second doping complementary to the first doping type, and a gate electrode arranged adjacent to the at least one body region and dielectrically insulated from the body region by a gate dielectric. The semiconductor arrangement also includes a further semiconductor device arranged in a second device region of the semiconductor body. The second device region includes a well-like structure of the second doping type surrounding a first semiconductor region of the first doping type. The further semiconductor device includes device regions arranged in the first semiconductor region.

Abstract: An embodiment of the invention provides a compound barrier layer, including: a first barrier layer disposed on a substrate; and a second barrier layer disposed on the first barrier layer, wherein the first barrier layer and second barrier layer both include a plurality of alternately arranged inorganic material regions and organo-silicon material regions and the inorganic material regions and the organo-silicon material regions of the first barrier layer and second barrier layer are alternatively stacked vertically.

Abstract: A first product may be provided that comprises a substrate having a first surface, a first side, and a first edge where the first surface meets the first side; and a device disposed over the substrate, the device having a second side, where at least a first portion of the second side is disposed within 3 mm from the first edge of the substrate. The first product may further comprise a first barrier film that covers at least a portion of the first edge of the substrate, at least a portion of the first side of the substrate, and at least the first portion of the second side of the device.

Abstract: An array substrate for a liquid crystal display (LCD) and manufacturing method thereof are provided. The array substrate for a liquid crystal display (LCD) includes: a substrate, including: a gate electrode, a pixel electrode, and a common electrode, a gate pad formed on the substrate, and connected to the gate electrode, a gate insulating layer formed on the gate pad, a first protective layer formed on the gate insulating layer, a second protective layer formed on the first protective layer, a first metal layer formed on the second protective layer, and connected to the gate pad through a first contact hole which exposes the gate pad, a third protective layer formed on the first metal layer and the second protective layer, and a second metal layer formed on the third protective layer, and connected to the first metal layer through a second contact hole which exposes the first metal layer.

Abstract: A semiconductor device comprising a circuit including a plurality of thin film transistors and at least one diode (D2a), wherein: the plurality of thin film transistors have the same conductivity type; when the conductivity type of the plurality of thin film transistors is an N type, a cathode-side electrode of the diode (D2a) is connected to a line (550) connected to a gate of a selected one of the plurality of thin film transistors; when the conductivity type of the plurality of thin film transistors, an anode-side electrode of the diode is connected to a line (550) connected to a gate of a selected one of the plurality of thin film transistors; and another diode arranged so that a current flow direction thereof is opposite to that of the diode (D2a) is not formed on the line (550). Thus, it is possible to suppress damage to a thin film transistor due to ESD while suppressing the increase in circuit scale from conventional techniques.

Abstract: Disclosed is a light-emitting device comprising: a light-emitting stack with a length and a width comprising: a first conductivity type semiconductor layer; an active layer on the first conductivity type semiconductor layer; and a second conductivity type semiconductor layer on the active layer; a conductive layer with a width greater than the width of the first conductivity type semiconductor layer and under the first conductivity type semiconductor layer, the conductive layer comprising a first overlapping portion which overlaps the first conductivity type semiconductor layer and a first extending portion which does not overlap the first conductivity type semiconductor layer; a transparent conductive layer with a width greater than the width of the second conductivity type semiconductor layer over the second conductivity type semiconductor layer, the transparent conductive layer comprising a second overlapping portion which overlaps the second conductivity type semiconductor layer and a second extending por

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; and a gate stack disposed on the semiconductor substrate. The gate stack includes a high k dielectric material layer, a capping layer disposed on the high k dielectric material layer, and a metal layer disposed on the capping layer. The capping layer and the high k dielectric material layer have a footing structure.