Abstract: There is provided a film forming method for forming a film on a target object having thereon an insulating layer 1 that is made of a low-k film and having a recess 2 whose bottom surface is exposed to a metallic layer 3. The film forming method includes forming a first-metal-containing film containing a first metal such as ruthenium (Ru); and after forming the first-metal-containing film, forming a second-metal-containing film containing a second metal such as a manganese (Mn) having a barrier property against a filling metal to be filled in the recess.

Abstract: The product of the breakdown voltage (BVCEO) and the cutoff frequency (fT) of a SiGe heterojunction bipolar transistor (HBT) is increased beyond the Johnson limit by utilizing a doped region with a hollow core that extends down from the base to the heavily-doped buried collector region. The doped region and the buried collector region have opposite dopant types.

Abstract: A structure and a process for a microelectromechanical system (MEMS)-based sensor are provided. The structure for a MEMS-based sensor includes a substrate chip. A first insulating layer covers a top surface of the substrate chip. A device layer is disposed on a top surface of the first insulating layer. The device layer includes a periphery region and a sensor component region. The periphery region and a sensor component region have an air trench therebetween. The component region includes an anchor component and a moveable component. A second insulating layer is disposed on a top surface of the device layer, bridging the periphery region and a portion of the anchor component. A conductive pattern is disposed on the second insulating layer, electrically connecting to the anchor component.

Abstract: In one embodiment, an interconnect structure between an integrated circuit (IC) chip and a substrate comprises a plurality of materials.

Abstract: A nonvolatile memory device (10A) comprises an upper electrode layer (2); a lower electrode layer (4); a resistance variable layer (3) sandwiched between the upper electrode layer (2) and the lower electrode layer (4); and a charge diffusion prevention mask (1A) formed on a portion of the upper electrode layer (2); wherein the resistance variable layer (3) includes a first film comprising oxygen-deficient transition metal oxide and a second film comprising oxygen-deficient transition metal oxide which is higher in oxygen content than the first film; at least one of the upper electrode layer (2) and the lower electrode layer (4) comprises a simple substance or alloy of a platinum group element; and the charge diffusion prevention mask (1A) is insulative, and is lower in etching rate of dry etching than the upper electrode layer (2) and the lower electrode layer (4).

Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.

Abstract: A light emitting device comprising a first common electrode (11; 21), a structured conducting layer (12; 22), forming a set of electrode pads (14; 24a, 24b) electrically isolated from each other, a dielectric layer (13; 23), interposed between the first common electrode layer (11; 21) and the structured conducting layer (12; 22), a second common electrode (15; 30), and a plurality of light emitting elements (16; 20a, 20b), each light emitting element being electrically connected between one of the electrode pads (14; 24a, 24b) and the second common electrode (15; 30), so as to be connected in series with a capacitor (18; 31) comprising one of the electrode pads (14; 24a, 24b), the dielectric layer (13; 23), and the first common electrode (11; 21). When an alternating voltage is applied between the first and second common electrodes, the light emitting elements will be powered through a capacitive coupling, also providing current limitation.

Abstract: A pnp SiGe heterojunction bipolar transistor (HBT) reduces the rate that p-type dopant atoms in the p+ emitter of the transistor out diffuse into a lowly-doped region of the base of the transistor by epitaxially growing the emitter to include a single-crystal germanium region and an overlying single-crystal silicon region.

Abstract: A semiconductor device includes a lead frame, a semiconductor element mounted on the lead frame, and a frame-like member formed on the lead frame, surrounding the semiconductor element, and covering a side surface of the lead frame and exposing a lower surface of the lead frame. The frame-like member has at least one concave portion in a side surface thereof. The concave portion has a ceiling portion located at the same height as or lower than an upper surface of the lead frame, and a bottom portion located higher than the lower surface of the lead frame.

Abstract: A fabricating process of circuit substrate sequently includes: providing a substrate with a pad and a dielectric stack layer disposed at the substrate and overlaying the pad, in which the stack layer includes two dielectric layers and a third dielectric layer located between the two dielectric layers, and the etching rate of the third dielectric layer is greater than the etching rate of the two dielectric layers; forming an opening corresponding to the pad at the stack layer; performing a wet etching process on the stack layer to remove the portion of the third dielectric layer surrounding the opening to form a gap between the portions of the two dielectric layers surrounding the opening; performing a plating process on the stack layer and the pad to respectively form two plating layers at the stack layer and the pad, in which the gap isolates the two plating layers from each other.