Abstract: A backside illumination image sensor structure comprises an image sensor formed adjacent to a first side of a semiconductor substrate, wherein a first dielectric layer formed over the first side of the semiconductor substrate and an interconnect layer formed over the first dielectric layer. The image sensor structure further comprises a backside illumination film formed over a second side of the semiconductor substrate and a first silicon halogen compound layer formed between the second side of the semiconductor substrate and the backside illumination film.

Abstract: A semiconductor device may include a substrate including an active region defined by a device isolation layer, gate electrodes extending in a first direction on the substrate and spaced apart from each other, gate tabs extending in a second direction different from the first direction and connecting adjacent gate electrodes to each other, the gate tabs spaced apart from each other, and a first contact plug disposed on the active region under a space confined by the adjacent gate electrodes and adjacent gate tabs. The space may include a first region having a first width and a second region having a second width smaller than the first width, the first contact plug may be disposed on the active region under the second region.

Abstract: A LED includes a red light emitting unit, a green light emitting unit, a blue light emitting unit, and an optical grating located on a same plane. The red light emitting unit, the green light emitting unit and the blue light emitting unit are located around the optical grating. Each light emitting unit includes a first substrate, a first semiconductor layer, an first active layer, a second semiconductor layer and a first reflector layer stacked in that order. The optical grating includes a second substrate, a first semiconductor layer, an active layer, and a second semiconductor layer stacked in that order. The second substrate and the three first substrates are a continuous integrated substrate structure.

Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.

Abstract: A semiconductor light-emitting device is provided. The semiconductor light-emitting device includes a buffer layer, a light-emitting layer, a first-conductivity semiconductor layer, a first light reflecting layer, a protective structure, and an adhesive layer. The first-conductivity semiconductor layer is disposed between the buffer layer and a first side of the light-emitting layer. The first light reflecting layer is disposed between the first-conductivity semiconductor layer and the buffer layer. The protective structure is disposed between the first reflecting layer and the buffer layer. The adhesive layer is disposed between the first-conductivity semiconductor layer and the protective structure.

Abstract: Integrated circuits that include resistors are provided. An integrated circuit resistor may include a conductive structure disposed over a semiconductor substrate. An oxide layer may be interposed between the conductive structure and a top surface of the semiconductor substrate. A shallow trench isolation structure may be formed in the substrate directly beneath the oxide layer. The shallow trench isolation structure may be formed in a given region in the substrate that is contained within a surrounding n-well and a deep n-well. The given region within which the shallow trench isolation structure is formed may exhibit native substrate dopant concentration levels; the given region is neither an n-well nor a p-well. The surrounding n-well and the deep n-well may be reversed biased to help fully deplete the given region so that parasitic capacitance levels associated with the resistor are minimized.

Abstract: A light-emitting element having extremely high efficiency of approximately 25% is provided. The light-emitting element includes a light-emitting layer which contains a phosphorescent guest, an n-type host, and a p-type host, where the light-emitting layer is interposed between an n-type layer including the n-type host and a p-type layer including the p-type host, and where the n-type host and the p-type host are able to form an exciplex in the light-emitting layer. The light-emitting element exhibits an extremely high emission efficiency (power efficiency of 74.3 lm/W, external quantum efficiency of 24.5%, energy efficiency of 19.3%) at a low driving voltage (2.6 V) at which luminance of 1200 cd/m2 is attainable.

Abstract: A white organic light emitting device and a display device using the same to which a 2-peak spectrum is applied to execute white display comprises a first electrode and a second electrode disposed opposite each other on a substrate, and a blue light emitting unit and a phosphorescent light emitting unit provided between the first electrode and the second electrode, and a 2-peak white spectrum is formed through a first light emitting peak of the blue light emitting unit at a wavelength of 430 nm to 460 nm and a second light emitting peak of the phosphorescent light emitting unit at a wavelength of 530 nm to 630 nm.

Abstract: A method for producing a light emitting diode device includes the steps of preparing a base board; allowing a light semiconductor layer where an electrode portion is provided at one side in a thickness direction to be disposed in opposed relation to the base board, and the electrode portion to be electrically connected to a terminal, so that the light semiconductor layer is flip-chip mounted on the base board; forming an encapsulating resin layer containing a light reflecting component at the other side of the base board so as to cover the light semiconductor layer and the electrode portion; removing the other side portion of the encapsulating resin layer so as to expose the light semiconductor layer; and forming a phosphor layer formed in a sheet state so as to be in contact with the other surface of the light semiconductor layer.

Abstract: A white LED includes a red light emitting unit, a green light emitting unit, a blue light emitting unit, and an optical grating located on a same plane. The red light emitting unit, the green light emitting unit and the blue light emitting unit are located around the optical grating. Each light emitting unit includes a first semiconductor layer, an active layer, a second semiconductor layer and a first reflector layer stacked in that order. The optical grating includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in that order. The first semiconductor layer of the optical grating and the first semiconductor layers of the light emitting units are a continuous integrated structure.

Abstract: A bonding structure includes a first member, a second member and a bonding member. The first member has a plate shape and is made of a carbon-base material. The first member serves as a heat diffusion member that transfers heat at least in a thickness direction, which is perpendicular to a plane of the plate shape. The second member is bonded to the first member through the bonding member. The first member has a metal thin film at least on an opposed surface that is opposed to the second member. The bonding member is disposed between the opposed surface of the first member and the second member. The bonding member is provided by a sintered body of metal particle. For example, the bonding structure is employed in a cooling unit including a heat source.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of insulative separating films, a channel body, and a memory film. The stacked body includes a plurality of electrode layers and a plurality of insulating layers. The plurality of insulative separating films separates the stacked body into a plurality. The channel body extends in the stacking direction between the plurality of insulative separating films. A width of the electrode layer of a lower layer side between the insulative separating film and the memory film is greater than a width of the electrode layer of an upper layer side between the insulative separating film and the memory film. An electrical resistivity of the electrode layer is higher for the electrode layer of the lower layer side having the greater width than for the electrode layer of the upper layer side having the lesser width.

Abstract: To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.

Abstract: A main package includes a plurality of stacked semiconductor chips and a plurality of first terminals associated with different ones of the semiconductor chips. An additional package includes an additional semiconductor chip and at least one second terminal electrically connected to the additional semiconductor chip. The additional semiconductor chip is to substitute for one of the plurality of semiconductor chips in the main package. The main package and the additional package are arranged in one of a plurality of relative positional relationships that is selected according to which one of the plurality of semiconductor chips in the main package is to be substituted with the additional semiconductor chip.

Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.

Abstract: Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.

Abstract: A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer.

Abstract: It is an object to provide an epitaxial silicon wafer that is provided with an excellent gettering ability in which a polysilicon layer is formed on the rear face side of a silicon crystal substrate into which phosphorus (P) and germanium (Ge) have been doped. A silicon epitaxial layer is grown by a CVD method on the surface of a silicon crystal substrate into which phosphorus and germanium have been doped at a high concentration. After that, a PBS forming step for growing a polysilicon layer is executed on the rear face side of a silicon crystal substrate. By the above steps, the number of LPDs (caused by an SF) that occur on the surface of the epitaxial silicon wafer due to the SF can be greatly reduced.

Abstract: A semiconductor device is manufactured by etching a semiconductor substrate including an active region, forming a bit line contact hole from which the active region is protruded, forming a first spacer exposing a top of the active region at each of an inner wall and a bottom of the bit line contact hole, forming a bit line contact plug and a bit line over the exposed active region, and forming a second spacer over the semiconductor substrate including not only the bit line contact plug but also the bit line.