Abstract: A semiconductor package includes a flip chip mounted on a plurality of leads and encapsulated by a molding compound. The upper surfaces of the leads includes a plurality of bump-bonding regions at the fan-in ends of the leads, and the lower surfaces of the leads include a plurality of outer connecting regions at the fan-out ends of the leads. A plurality of indentations are formed at the upper surfaces of the leads and adjacent to the corresponding bump-bonding regions so as to avoid solder contamination on the leads. After molding, the indentations are filled with the molding compound. Preferably, the indentations have a reversed “?”-shaped profile to prevent bumps of the flip chip from excessively wetting over the other portions of the leads to firmly fix the fan-in ends of the leads.

Abstract: In one example embodiment, a transistor (100) is provided. The transistor (100) comprises a source (10), a gate (30), a drain (20), and a field plate (40) located between the gate (30) and the drain (20). The field plate (40) comprises a plurality of connection locations (47) and a plurality of electrical connectors (45) connecting said plurality of connection locations (47) to a potential.

Abstract: An interposer for use in an external lead or land pattern semiconductor package. The interposer includes an interposer body which is molded from a dielectric material. The interposer body defines opposed top and bottom surfaces, an outer peripheral edge, and an inner peripheral edge. Embedded within the interposer body is a die pad which itself defines opposed top and bottom surfaces and a peripheral edge. The bottom surface of the die pad is exposed in and substantially flush with the bottom surface of the interposer body, with the inner peripheral edge of the interposer body and the top surface of the die pad collectively defining a cavity of the interposer. A plurality of electrically conductive interposer leads are embedded within the top surface of the interposer body and at least partially exposed therein. The interposer body forms a nonconductive barrier between each of the interposer leads and between the interposer leads and the die pad.

Abstract: A method of manufacturing a data carrier from a support strip includes an overmoulding step, in which at least one support element of the support strip is overmoulded so as to obtain a data carrier body, and a microcircuit-connecting step, in which a microcircuit is electrically connected to the wiring pads of the data carrier body so as to obtain the data carrier.

Abstract: By securing a fatigue life of a connection portion with a semiconductor package and a mount board, a semiconductor device having a high reliability is provided. The semiconductor device consists of a semiconductor element, a mount board in which said semiconductor element is mounted, and a support member in which said mount board is supported through a connection member, wherein the connection member consists of a first mount board connection portion with the mount board at a first side of the element in a direction along a main surface of the mount board in which the semiconductor element is mounted, and consists of a first support member connection portion with the support member at a second side in opposition to the first side through the semiconductor element.

Abstract: A lead frame structure includes: at least a die pad for mounting a semiconductor chip thereon; a plurality of suspension members mechanically connected with the die pad; and a plurality of supporting members. Each supporting member has a connection region mechanically connected with each of the plurality of suspension members for mechanically supporting the at least die pad via the plurality of suspension pins. The connection region of the supporting member has a penetrating opening portion which provides a mechanical flexibility to the connection region and which allows the connection region to be deformed toward the suspension member upon application of a tensile stress to the suspension member in a down-set process.

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: In a composite device of the laminate type having a laminate structure of a composite ceramic layer and a dielectric ceramic layer, the composite ceramic layer including a layer portion having the same composition as the dielectric ceramic layer and a plurality of particle portions formed on the surface of the layer portion. The particle portions are made from magnetic ceramic material. This prevents the ceramic layers of the device from cracking and separating when fired.

Abstract: A semiconductor device comprises a semiconductor element which is flip-chip bonded to a circuit substrate. The semiconductor element and the circuit substrate are flip-chip bonded using a sealing resin having flux function. The semiconductor element includes a solder bump formed on a first electrode pad through a first low melting point solder layer. The circuit substrate includes a second electrode pad corresponding to the first electrode pad, and a second low melting point solder layer is formed on the second electrode pad. The solder bump is bonded to the first and second electrode pads through the first and second low melting point solder layers.

Abstract: An integrated circuit device and method thereof includes a substrate and a plurality of microelectronic devices. Each of the microelectronics devices includes a patterned feature located over the substrate, wherein the pattern feature comprises at least one electrical contact. The integrated circuit also includes a plurality of interconnect layers for distributing electrical power to the plurality of microelectronic devices. The interconnect layers include a plurality of conductive members associated with each interconnect layer, wherein the members of at least one subsequent interconnect layer straddle members of at least one adjacent interconnect layer. The integrated circuit device further includes a plurality of bond pads connected to at least one of the plurality of members of the interconnect layers.

Abstract: A plurality of semiconductor chips (14) each having a first main surface (14b) formed with electrode pads (21) and a second main surface (14c) opposite to the first main surface are respectively mounted on a chip mounting surface (12a) larger in area than the second main surface, of a wafer-shaped mounting substrate (12) at equal intervals so as to extend along first and second trenches (18a, 18b) defined in the chip mounting surface with these trenches as target lines. Thereafter, solder balls (25) electrically connected to the electrode pads of the semiconductor chips are disposed on their corresponding wiring patterns 34 that extend from above first regions (100) located above the semiconductor chips, of a surface region of an encapsulating layer (32) covering the semiconductor chips to above second regions (200) that surround the first regions. Afterwards, the encapsulating layer and the mounting substrate are cut and thereby fractionized into semiconductor devices each having a fan-out structure.

Abstract: Provided is a semiconductor device which prevents displacement of a semiconductor element and a wiring pattern of a wiring substrate so as to ensure the connection of the semiconductor element and the wiring pattern. The semiconductor device of the present invention includes a semiconductor element and a wiring substrate which is provided with a film substrate and a wiring pattern which is formed on the film substrate, the semiconductor element is connected to the wiring pattern, and the semiconductor element and the wiring substrate are sealed with a resin. A metallic film, made of material having a smaller coefficient of linear thermal expansion than the film substrate, is formed in a region where the wiring pattern is not formed on at least one surface of the film substrate.

Abstract: In a wiring substrate of the present invention in which a bump of an electronic parts is bonded to a connection pad of a wiring pattern provided on an insulating film by an ultrasonic flip-chip packaging, a via hole into which a via post acting as a strut to support the connection pad upon the ultrasonic flip-chip packaging is filled is arranged in the insulating film under the connection pad.

Abstract: The present invention provides a COF flexible printed wiring board whose insulating layer is not melt-adhered to a heating tool, to thereby enhance reliability and productivity of a semiconductor chip mounting line, and also provides a method of producing the COF flexible printed wiring board. The COF flexible printed wiring board contains an insulating layer, a wiring pattern, on which a semiconductor chip being mounted, formed of a conductor layer provided on at least one side of the insulating layer and a releasing layer, wherein the releasing layer is formed from a releasing agent containing at least one species selected from a silane compound and silica sol and is provided on a surface of the insulating layer, which is opposite to the mounting side of the semiconductor chip.

Abstract: An LED assembly includes a heat sink and a submount. The heat sink has a top mating surface that is solder wettable, and the submount has a bottom mating surface that is solder wettable. The top and the bottom mating surfaces have substantially the same shape and area. The submount is soldered atop the heat sink. During solder reflow, the molten solder causes the submount to align with the top mating surface of the heat sink. The LED assembly may further include a substrate having a top mating surface, and the heat sink may further include a bottom mating surface. The top and bottom mating surfaces have substantially the same shape and area. The heat sink is soldered atop the substrate. During solder reflow, the molten solder causes the heat sink to align with the top mating surface of the substrate.

Abstract: Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.

Abstract: A SiP type semiconductor device and a method of producing the same is provided wherein curvature of a wafer is suppressed in the production steps, workability does not decline, and high throughput can be attained. An insulation layer is formed by stacking a plurality of resin layers on a semiconductor substrate, wiring layers are formed by being buried in the insulation layer so as to be connected to an electronic circuit, an insulating buffer layer for buffering a stress generated at the time of being mounted on a board is formed on the insulation layer, a conductive post is formed through the buffer layer and connected to the wiring layer, and a projecting electrode is formed projecting from a surface of the buffer layer and connected to the conductive post.

Abstract: A semiconductor chip includes a semiconductor substrate including first and second surfaces and a plurality of side surfaces, the first and second surfaces being parallel to each other and facing in opposite directions, the side surfaces connecting peripheries of the first and second surfaces. At least one of the side surfaces is an inclined surface with respect to the first and second surfaces, and a groove is formed in the inclined surface. The groove extends in a direction which intersects a plane parallel to the first and second surfaces and extends in a direction which intersects a plane which intersects the first and second surfaces at right angles.

Abstract: A semiconductor device with excellent heat dissipation characteristics that can achieve a high reliability when mounted in electronic equipment such as a cellular phone or the like and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of semiconductor chips mounted on the substrate by stacking one on top of another, and an encapsulation resin layer made of encapsulation resin. Among the plurality of semiconductor chips, a first semiconductor chip as an uppermost semiconductor chip is mounted with a surface thereof on which a circuit is formed facing toward the substrate, and the encapsulation resin layer is formed so that at least a surface of the first semiconductor chip opposite to the surface on which the circuit is formed and a part of side surfaces of the first semiconductor chip are exposed to the outside of the encapsulation resin layer.